Change in ...coreboot[master]: coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)

[Julius Werner (Code Review)]

Hello Aaron Durbin, Patrick Georgi,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/31774

to review the following change.

Change subject: coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)
......................................................................

coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)

This patch is a raw application of

find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'

Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner 
---
M src/arch/arm/armv7/mmu.c
M src/arch/arm/include/arch/memlayout.h
M src/arch/arm/include/armv7/arch/cache.h
M src/arch/arm/tables.c
M src/arch/arm64/arm_tf.c
M src/arch/arm64/armv8/exception.c
M src/arch/arm64/boot.c
M src/arch/arm64/include/armv8/arch/barrier.h
M src/arch/arm64/tables.c
M src/arch/mips/bootblock_simple.c
M src/arch/ppc64/include/arch/cpu.h
M src/arch/riscv/include/arch/cpu.h
M src/arch/riscv/sbi.c
M src/arch/x86/acpi.c
M src/arch/x86/acpi_device.c
M src/arch/x86/acpi_s3.c
M src/arch/x86/assembly_entry.S
M src/arch/x86/bootblock.ld
M src/arch/x86/bootblock_crt0.S
M src/arch/x86/bootblock_romcc.S
M src/arch/x86/bootblock_simple.c
M src/arch/x86/c_start.S
M src/arch/x86/car.ld
M src/arch/x86/cbmem.c
M src/arch/x86/cpu.c
M src/arch/x86/exception.c
M src/arch/x86/exit_car.S
M src/arch/x86/gdt.c
M src/arch/x86/include/arch/acpi.h
M src/arch/x86/include/arch/cpu.h
M src/arch/x86/include/arch/early_variables.h
M src/arch/x86/include/arch/exception.h
M src/arch/x86/include/arch/interrupt.h
M src/arch/x86/include/arch/pci_io_cfg.h
M src/arch/x86/include/arch/registers.h
M src/arch/x86/include/arch/smp/spinlock.h
M src/arch/x86/include/cf9_reset.h
M src/arch/x86/ioapic.c
M src/arch/x86/memlayout.ld
M src/arch/x86/pci_ops_conf1.c
M src/arch/x86/pirq_routing.c
M src/arch/x86/postcar_loader.c
M src/arch/x86/smbios.c
M src/arch/x86/tables.c
M src/arch/x86/timestamp.c
M src/commonlib/cbfs.c
M src/commonlib/include/commonlib/stdlib.h
M src/commonlib/storage/mmc.c
M src/commonlib/storage/sd_mmc.c
M src/commonlib/storage/sd_mmc.h
M src/commonlib/storage/sdhci.c
M src/commonlib/storage/sdhci_display.c
M src/commonlib/storage/storage.c
M src/console/console.c
M src/console/init.c
M src/console/post.c
M src/console/printk.c
M src/console/vtxprintf.c
M src/cpu/amd/agesa/family12/model_12_init.c
M src/cpu/amd/agesa/family14/model_14_init.c
M src/cpu/amd/agesa/family15tn/model_15_init.c
M src/cpu/amd/agesa/family16kb/model_16_init.c
M src/cpu/amd/car/cache_as_ram.inc
M src/cpu/amd/car/disable_cache_as_ram.c
M src/cpu/amd/car/post_cache_as_ram.c
M src/cpu/amd/family_10h-family_15h/fidvid.c
M src/cpu/amd/family_10h-family_15h/init_cpus.c
M src/cpu/amd/family_10h-family_15h/model_10xxx_init.c
M src/cpu/amd/family_10h-family_15h/powernow_acpi.c
M src/cpu/amd/family_10h-family_15h/ram_calc.c
M src/cpu/amd/microcode/microcode.c
M src/cpu/amd/pi/00630F01/fixme.c
M src/cpu/amd/pi/00630F01/model_15_init.c
M src/cpu/amd/pi/00660F01/fixme.c
M src/cpu/amd/pi/00660F01/model_15_init.c
M src/cpu/amd/pi/00730F01/fixme.c
M src/cpu/amd/pi/00730F01/model_16_init.c
M src/cpu/amd/quadcore/quadcore.c
M src/cpu/intel/car/non-evict/cache_as_ram.S
M src/cpu/intel/car/p4-netburst/cache_as_ram.S
M src/cpu/intel/car/romstage.c
M src/cpu/intel/common/common_init.c
M src/cpu/intel/fsp_model_406dx/model_406dx_init.c
M src/cpu/intel/haswell/bootblock.c
M src/cpu/intel/haswell/romstage.c
M src/cpu/intel/hyperthreading/intel_sibling.c
M src/cpu/intel/model_1067x/mp_init.c
M src/cpu/intel/model_2065x/bootblock.c
M src/cpu/intel/model_206ax/bootblock.c
M src/cpu/intel/model_f3x/model_f3x_init.c
M src/cpu/intel/smm/gen1/smmrelocate.c
M src/cpu/intel/turbo/turbo.c
M src/cpu/x86/16bit/entry16.inc
M src/cpu/x86/32bit/entry32.inc
M src/cpu/x86/backup_default_smm.c
M src/cpu/x86/car.c
M src/cpu/x86/lapic/apic_timer.c
M src/cpu/x86/lapic/boot_cpu.c
M src/cpu/x86/lapic/lapic_cpu_init.c
M src/cpu/x86/mp_init.c
M src/cpu/x86/mtrr/debug.c
M src/cpu/x86/mtrr/mtrr.c
M src/cpu/x86/sipi_vector.S
M src/cpu/x86/smm/smihandler.c
M src/cpu/x86/smm/smm_module_handler.c
M src/cpu/x86/smm/smm_module_loader.c
M src/cpu/x86/smm/smmhandler.S
M src/cpu/x86/smm/smmrelocate.S
M src/cpu/x86/tsc/delay_tsc.c
M src/device/device.c
M src/device/device_const.c
M src/device/oprom/include/io.h
M src/device/oprom/include/x86emu/fpu_regs.h
M src/device/oprom/include/x86emu/regs.h
M src/device/oprom/include/x86emu/x86emu.h
M src/device/oprom/realmode/x86.c
M src/device/oprom/realmode/x86_interrupts.c
M src/device/oprom/yabel/biosemu.c
M src/device/oprom/yabel/compat/functions.c
M src/device/oprom/yabel/debug.h
M src/device/oprom/yabel/device.c
M src/device/oprom/yabel/device.h
M src/device/oprom/yabel/interrupt.c
M src/device/oprom/yabel/io.c
M src/device/oprom/yabel/mem.c
M src/device/oprom/yabel/vbe.c
M src/device/pci_device.c
M src/device/pci_rom.c
M src/device/pciexp_device.c
M src/device/root_device.c
M src/drivers/amd/agesa/acpi_tables.c
M src/drivers/amd/agesa/cache_as_ram.S
M src/drivers/amd/agesa/def_callouts.c
M src/drivers/amd/agesa/eventlog.c
M src/drivers/amd/agesa/heapmanager.c
M src/drivers/amd/agesa/oem_s3.c
M src/drivers/amd/agesa/romstage.c
M src/drivers/amd/agesa/state_machine.c
M src/drivers/elog/boot_count.c
M src/drivers/elog/elog.c
M src/drivers/emulation/qemu/bochs.c
M src/drivers/emulation/qemu/cirrus.c
M src/drivers/generic/adau7002/adau7002.c
M src/drivers/generic/generic/chip.h
M src/drivers/generic/max98357a/max98357a.c
M src/drivers/i2c/da7219/da7219.c
M src/drivers/i2c/designware/dw_i2c.c
M src/drivers/i2c/designware/dw_i2c.h
M src/drivers/i2c/generic/generic.c
M src/drivers/i2c/hid/hid.c
M src/drivers/i2c/nau8825/nau8825.c
M src/drivers/i2c/tpm/tis.c
M src/drivers/i2c/tpm/tis_atmel.c
M src/drivers/i2c/w83795/w83795.c
M src/drivers/intel/fsp1_0/cache_as_ram.inc
M src/drivers/intel/fsp1_0/fastboot_cache.c
M src/drivers/intel/fsp1_0/fsp_util.c
M src/drivers/intel/fsp1_0/fsp_util.h
M src/drivers/intel/fsp1_1/after_raminit.S
M src/drivers/intel/fsp1_1/cache_as_ram.inc
M src/drivers/intel/fsp1_1/fsp_util.c
M src/drivers/intel/fsp1_1/raminit.c
M src/drivers/intel/fsp1_1/ramstage.c
M src/drivers/intel/fsp1_1/romstage.c
M src/drivers/intel/fsp1_1/stack.c
M src/drivers/intel/fsp1_1/vbt.c
M src/drivers/intel/fsp2_0/debug.c
M src/drivers/intel/fsp2_0/hand_off_block.c
M src/drivers/intel/fsp2_0/include/fsp/soc_binding.h
M src/drivers/intel/fsp2_0/memory_init.c
M src/drivers/intel/fsp2_0/silicon_init.c
M src/drivers/intel/fsp2_0/util.c
M src/drivers/intel/gma/int15.h
M src/drivers/intel/gma/opregion.c
M src/drivers/intel/gma/vbt.c
M src/drivers/intel/wifi/wifi.c
M src/drivers/lenovo/wacom.c
M src/drivers/mrc_cache/mrc_cache.c
M src/drivers/net/r8168.c
M src/drivers/pc80/pc/i8254.c
M src/drivers/pc80/rtc/mc146818rtc.c
M src/drivers/pc80/rtc/mc146818rtc_boot.c
M src/drivers/pc80/rtc/mc146818rtc_romcc.c
M src/drivers/pc80/tpm/tis.c
M src/drivers/siemens/nc_fpga/nc_fpga.c
M src/drivers/smmstore/store.c
M src/drivers/spi/adesto.c
M src/drivers/spi/amic.c
M src/drivers/spi/atmel.c
M src/drivers/spi/eon.c
M src/drivers/spi/gigadevice.c
M src/drivers/spi/macronix.c
M src/drivers/spi/spansion.c
M src/drivers/spi/spi_flash.c
M src/drivers/spi/sst.c
M src/drivers/spi/stmicro.c
M src/drivers/spi/winbond.c
M src/drivers/tpm/tpm.c
M src/drivers/uart/uart8250io.c
M src/drivers/uart/uart8250mem.c
M src/drivers/uart/util.c
M src/drivers/usb/ehci_debug.c
M src/drivers/usb/gadget.c
M src/drivers/xgi/common/vb_init.c
M src/drivers/xgi/common/xgi_coreboot.c
M src/drivers/xgi/z9s/z9s.c
M src/ec/google/chromeec/acpi/ec.asl
M src/ec/google/chromeec/ec.c
M src/ec/google/chromeec/ec_i2c.c
M src/ec/google/chromeec/ec_lpc.c
M src/ec/google/chromeec/smihandler.c
M src/ec/google/chromeec/switches.c
M src/ec/google/wilco/acpi/superio.asl
M src/ec/google/wilco/bootblock.c
M src/ec/kontron/kempld/early_kempld.c
M src/ec/lenovo/h8/h8.c
M src/ec/lenovo/h8/panic.c
M src/ec/quanta/ene_kb3940q/ec.c
M src/include/adainit.h
M src/include/assert.h
M src/include/bootstate.h
M src/include/cbmem.h
M src/include/console/cbmem_console.h
M src/include/console/console.h
M src/include/console/flash.h
M src/include/console/ne2k.h
M src/include/console/qemu_debugcon.h
M src/include/console/spi.h
M src/include/console/spkmodem.h
M src/include/console/uart.h
M src/include/console/usb.h
M src/include/cper.h
M src/include/cpu/x86/lapic.h
M src/include/cpu/x86/msr.h
M src/include/cpu/x86/post_code.h
M src/include/cpu/x86/smm.h
M src/include/cpu/x86/tsc.h
M src/include/device/device.h
M src/include/device/dram/common.h
M src/include/device/dram/ddr3.h
M src/include/device/early_smbus.h
M src/include/device/pci.h
M src/include/device/pci_ehci.h
M src/include/device/pci_mmio_cfg.h
M src/include/device/smbus.h
M src/include/elog.h
M src/include/gic.h
M src/include/memlayout.h
M src/include/option.h
M src/include/pc80/mc146818rtc.h
M src/include/reg_script.h
M src/include/rmodule.h
M src/include/rules.h
M src/include/smp/atomic.h
M src/include/smp/node.h
M src/include/smp/spinlock.h
M src/include/stddef.h
M src/include/thread.h
M src/include/timer.h
M src/include/timestamp.h
M src/include/trace.h
M src/include/watchdog.h
M src/lib/bootblock.c
M src/lib/bootmode.c
M src/lib/cbfs.c
M src/lib/cbmem_console.c
M src/lib/coreboot_table.c
M src/lib/decompressor.c
M src/lib/edid.c
M src/lib/fallback_boot.c
M src/lib/gcov-glue.c
M src/lib/hardwaremain.c
M src/lib/imd_cbmem.c
M src/lib/libgcc.c
M src/lib/malloc.c
M src/lib/prog_loaders.c
M src/lib/program.ld
M src/lib/ramtest.c
M src/lib/reg_script.c
M src/lib/reset.c
M src/lib/spd_bin.c
M src/lib/timestamp.c
M src/mainboard/advansus/a785e-i/get_bus_conf.c
M src/mainboard/advansus/a785e-i/romstage.c
M src/mainboard/amd/bettong/BiosCallOuts.c
M src/mainboard/amd/bettong/romstage.c
M src/mainboard/amd/bimini_fam10/get_bus_conf.c
M src/mainboard/amd/bimini_fam10/romstage.c
M src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c
M src/mainboard/amd/lamar/BiosCallOuts.c
M src/mainboard/amd/lamar/OemCustomize.c
M src/mainboard/amd/mahogany_fam10/get_bus_conf.c
M src/mainboard/amd/mahogany_fam10/romstage.c
M src/mainboard/amd/olivehill/BiosCallOuts.c
M src/mainboard/amd/olivehill/OemCustomize.c
M src/mainboard/amd/olivehillplus/BiosCallOuts.c
M src/mainboard/amd/parmer/BiosCallOuts.c
M src/mainboard/amd/parmer/OemCustomize.c
M src/mainboard/amd/parmer/buildOpts.c
M src/mainboard/amd/serengeti_cheetah_fam10/mptable.c
M src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
M src/mainboard/amd/thatcher/BiosCallOuts.c
M src/mainboard/amd/thatcher/buildOpts.c
M src/mainboard/amd/tilapia_fam10/get_bus_conf.c
M src/mainboard/amd/tilapia_fam10/romstage.c
M src/mainboard/amd/torpedo/Oem.h
M src/mainboard/amd/torpedo/platform_cfg.h
M src/mainboard/apple/macbook21/gpio.c
M src/mainboard/apple/macbook21/hda_verb.c
M src/mainboard/asrock/g41c-gs/acpi/ich7_pci_irqs.asl
M src/mainboard/asrock/g41c-gs/romstage.c
M src/mainboard/asrock/imb-a180/OemCustomize.c
M src/mainboard/asus/am1i-a/BiosCallOuts.c
M src/mainboard/asus/am1i-a/OemCustomize.c
M src/mainboard/asus/f2a85-m/BiosCallOuts.c
M src/mainboard/asus/f2a85-m/OemCustomize.c
M src/mainboard/asus/f2a85-m/acpi/routing.asl
M src/mainboard/asus/f2a85-m/buildOpts.c
M src/mainboard/asus/f2a85-m/romstage.c
M src/mainboard/asus/kcma-d8/acpi_tables.c
M src/mainboard/asus/kcma-d8/bootblock.c
M src/mainboard/asus/kcma-d8/mptable.c
M src/mainboard/asus/kcma-d8/romstage.c
M src/mainboard/asus/kfsn4-dre/acpi_tables.c
M src/mainboard/asus/kfsn4-dre/bootblock.c
M src/mainboard/asus/kfsn4-dre/get_bus_conf.c
M src/mainboard/asus/kfsn4-dre/romstage.c
M src/mainboard/asus/kgpe-d16/acpi_tables.c
M src/mainboard/asus/kgpe-d16/bootblock.c
M src/mainboard/asus/kgpe-d16/mptable.c
M src/mainboard/asus/kgpe-d16/romstage.c
M src/mainboard/asus/m4a78-em/get_bus_conf.c
M src/mainboard/asus/m4a78-em/romstage.c
M src/mainboard/asus/m4a785-m/get_bus_conf.c
M src/mainboard/asus/m4a785-m/romstage.c
M src/mainboard/asus/m5a88-v/get_bus_conf.c
M src/mainboard/asus/m5a88-v/romstage.c
M src/mainboard/asus/p5qpl-am/romstage.c
M src/mainboard/avalue/eax-785e/get_bus_conf.c
M src/mainboard/avalue/eax-785e/romstage.c
M src/mainboard/bap/ode_e20XX/BiosCallOuts.c
M src/mainboard/bap/ode_e20XX/OemCustomize.c
M src/mainboard/bap/ode_e21XX/BiosCallOuts.c
M src/mainboard/biostar/a68n_5200/BiosCallOuts.c
M src/mainboard/biostar/a68n_5200/OemCustomize.c
M src/mainboard/biostar/a68n_5200/romstage.c
M src/mainboard/biostar/am1ml/BiosCallOuts.c
M src/mainboard/biostar/am1ml/OemCustomize.c
M src/mainboard/cavium/cn8100_sff_evb/bootblock.c
M src/mainboard/compulab/intense_pc/gpio.c
M src/mainboard/compulab/intense_pc/romstage.c
M src/mainboard/emulation/qemu-i440fx/northbridge.c
M src/mainboard/emulation/qemu-power8/bootblock.c
M src/mainboard/foxconn/g41s-k/acpi/superio.asl
M src/mainboard/foxconn/g41s-k/hda_verb.c
M src/mainboard/foxconn/g41s-k/romstage.c
M src/mainboard/gigabyte/ma785gm/get_bus_conf.c
M src/mainboard/gigabyte/ma785gm/romstage.c
M src/mainboard/gigabyte/ma785gmt/get_bus_conf.c
M src/mainboard/gigabyte/ma785gmt/romstage.c
M src/mainboard/gigabyte/ma78gm/get_bus_conf.c
M src/mainboard/gigabyte/ma78gm/romstage.c
M src/mainboard/gizmosphere/gizmo2/BiosCallOuts.c
M src/mainboard/gizmosphere/gizmo2/OemCustomize.c
M src/mainboard/google/auron/acpi/mainboard.asl
M src/mainboard/google/auron/smihandler.c
M src/mainboard/google/auron/variants/buddy/variant.c
M src/mainboard/google/beltino/acpi_tables.c
M src/mainboard/google/beltino/lan.c
M src/mainboard/google/butterfly/mainboard.c
M src/mainboard/google/butterfly/romstage.c
M src/mainboard/google/cyan/acpi/dptf.asl
M src/mainboard/google/cyan/acpi_tables.c
M src/mainboard/google/cyan/chromeos.c
M src/mainboard/google/cyan/dsdt.asl
M src/mainboard/google/cyan/ec.c
M src/mainboard/google/cyan/romstage.c
M src/mainboard/google/cyan/smihandler.c
M src/mainboard/google/cyan/spd/spd.c
M src/mainboard/google/dragonegg/dsdt.asl
M src/mainboard/google/foster/chromeos.c
M src/mainboard/google/gale/mainboard.c
M src/mainboard/google/gale/verstage.c
M src/mainboard/google/glados/mainboard.c
M src/mainboard/google/glados/romstage.c
M src/mainboard/google/glados/smihandler.c
M src/mainboard/google/gru/board.h
M src/mainboard/google/gru/boardid.c
M src/mainboard/google/gru/bootblock.c
M src/mainboard/google/gru/chromeos.c
M src/mainboard/google/gru/mainboard.c
M src/mainboard/google/gru/pwm_regulator.c
M src/mainboard/google/gru/romstage.c
M src/mainboard/google/gru/sdram_configs.c
M src/mainboard/google/hatch/dsdt.asl
M src/mainboard/google/jecht/lan.c
M src/mainboard/google/jecht/led.c
M src/mainboard/google/jecht/romstage.c
M src/mainboard/google/jecht/smihandler.c
M src/mainboard/google/kahlee/OemCustomize.c
M src/mainboard/google/kahlee/bootblock/bootblock.c
M src/mainboard/google/kahlee/smihandler.c
M src/mainboard/google/kahlee/variants/baseboard/mainboard.c
M src/mainboard/google/kukui/boardid.c
M src/mainboard/google/kukui/romstage.c
M src/mainboard/google/link/acpi_tables.c
M src/mainboard/google/link/mainboard.c
M src/mainboard/google/link/mainboard_smi.c
M src/mainboard/google/nyan/romstage.c
M src/mainboard/google/nyan_big/romstage.c
M src/mainboard/google/nyan_blaze/romstage.c
M src/mainboard/google/oak/bootblock.c
M src/mainboard/google/oak/gpio.h
M src/mainboard/google/oak/mainboard.c
M src/mainboard/google/octopus/romstage.c
M src/mainboard/google/octopus/variants/baseboard/memory.c
M src/mainboard/google/octopus/variants/baseboard/nhlt.c
M src/mainboard/google/parrot/acpi_tables.c
M src/mainboard/google/parrot/smihandler.c
M src/mainboard/google/poppy/dsdt.asl
M src/mainboard/google/rambi/mainboard.c
M src/mainboard/google/rambi/mainboard_smi.c
M src/mainboard/google/rambi/variants/ninja/lan.c
M src/mainboard/google/rambi/variants/sumo/lan.c
M src/mainboard/google/reef/smihandler.c
M src/mainboard/google/reef/variants/baseboard/nhlt.c
M src/mainboard/google/reef/variants/snappy/mainboard.c
M src/mainboard/google/sarien/dsdt.asl
M src/mainboard/google/sarien/variants/sarien/ramstage.c
M src/mainboard/google/slippy/acpi_tables.c
M src/mainboard/google/slippy/smihandler.c
M src/mainboard/google/smaug/mainboard.c
M src/mainboard/google/storm/mainboard.c
M src/mainboard/google/stout/acpi_tables.c
M src/mainboard/google/stout/ec.c
M src/mainboard/google/urara/mainboard.c
M src/mainboard/google/veyron/boardid.c
M src/mainboard/google/veyron/bootblock.c
M src/mainboard/google/veyron_mickey/bootblock.c
M src/mainboard/google/veyron_rialto/bootblock.c
M src/mainboard/hp/abm/OemCustomize.c
M src/mainboard/hp/compaq_8200_elite_sff/mainboard.c
M src/mainboard/hp/compaq_8200_elite_sff/romstage.c
M src/mainboard/hp/dl165_g6_fam10/mptable.c
M src/mainboard/hp/dl165_g6_fam10/romstage.c
M src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c
M src/mainboard/hp/pavilion_m6_1035dx/OemCustomize.c
M src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c
M src/mainboard/iei/kino-780am2-fam10/get_bus_conf.c
M src/mainboard/iei/kino-780am2-fam10/romstage.c
M src/mainboard/intel/apollolake_rvp/romstage.c
M src/mainboard/intel/baskingridge/acpi_tables.c
M src/mainboard/intel/bayleybay_fsp/mainboard.c
M src/mainboard/intel/bayleybay_fsp/romstage.c
M src/mainboard/intel/camelbackmountain_fsp/mainboard.c
M src/mainboard/intel/cannonlake_rvp/dsdt.asl
M src/mainboard/intel/cannonlake_rvp/spd/spd_util.c
M src/mainboard/intel/cannonlake_rvp/variants/baseboard/gpio.c
M src/mainboard/intel/cannonlake_rvp/variants/baseboard/nhlt.c
M src/mainboard/intel/coffeelake_rvp/dsdt.asl
M src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c
M src/mainboard/intel/coffeelake_rvp/variants/baseboard/nhlt.c
M src/mainboard/intel/dcp847ske/acpi/superio.asl
M src/mainboard/intel/dcp847ske/early_southbridge.c
M src/mainboard/intel/dcp847ske/romstage.c
M src/mainboard/intel/galileo/gpio.c
M src/mainboard/intel/galileo/mainboard.c
M src/mainboard/intel/galileo/vboot.c
M src/mainboard/intel/glkrvp/boardid.c
M src/mainboard/intel/glkrvp/ec.c
M src/mainboard/intel/glkrvp/romstage.c
M src/mainboard/intel/glkrvp/smihandler.c
M src/mainboard/intel/glkrvp/variants/baseboard/boardid.c
M src/mainboard/intel/glkrvp/variants/baseboard/gpio.c
M src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/gpio.h
M src/mainboard/intel/glkrvp/variants/baseboard/nhlt.c
M src/mainboard/intel/harcuvar/romstage.c
M src/mainboard/intel/icelake_rvp/acpi/mainboard.asl
M src/mainboard/intel/icelake_rvp/board_id.c
M src/mainboard/intel/icelake_rvp/dsdt.asl
M src/mainboard/intel/kblrvp/acpi/ec.asl
M src/mainboard/intel/kblrvp/acpi/mainboard.asl
M src/mainboard/intel/kblrvp/chromeos.c
M src/mainboard/intel/kblrvp/dsdt.asl
M src/mainboard/intel/kblrvp/hda_verb.c
M src/mainboard/intel/kblrvp/mainboard.c
M src/mainboard/intel/kblrvp/ramstage.c
M src/mainboard/intel/kblrvp/romstage.c
M src/mainboard/intel/kblrvp/smihandler.c
M src/mainboard/intel/kunimitsu/smihandler.c
M src/mainboard/intel/strago/ec.c
M src/mainboard/intel/strago/smihandler.c
M src/mainboard/jetway/pa78vm5/get_bus_conf.c
M src/mainboard/jetway/pa78vm5/romstage.c
M src/mainboard/kontron/ktqm77/mainboard.c
M src/mainboard/lenovo/g505s/BiosCallOuts.c
M src/mainboard/lenovo/g505s/OemCustomize.c
M src/mainboard/lenovo/g505s/buildOpts.c
M src/mainboard/lenovo/s230u/romstage.c
M src/mainboard/msi/ms7721/BiosCallOuts.c
M src/mainboard/msi/ms7721/OemCustomize.c
M src/mainboard/msi/ms7721/buildOpts.c
M src/mainboard/msi/ms7721/romstage.c
M src/mainboard/msi/ms9652_fam10/get_bus_conf.c
M src/mainboard/msi/ms9652_fam10/romstage.c
M src/mainboard/ocp/monolake/mainboard.c
M src/mainboard/ocp/wedge100s/mainboard.c
M src/mainboard/ocp/wedge100s/romstage.c
M src/mainboard/opencellular/elgon/bootblock.c
M src/mainboard/pcengines/apu2/BiosCallOuts.c
M src/mainboard/pcengines/apu2/mainboard.c
M src/mainboard/pcengines/apu2/romstage.c
M src/mainboard/samsung/lumpy/acpi_tables.c
M src/mainboard/samsung/lumpy/romstage.c
M src/mainboard/samsung/stumpy/romstage.c
M src/mainboard/scaleway/tagada/bootblock.c
M src/mainboard/siemens/mc_bdx1/mainboard.c
M src/mainboard/siemens/mc_tcu3/mainboard.c
M src/mainboard/sifive/hifive-unleashed/romstage.c
M src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c
M src/mainboard/supermicro/h8dmr_fam10/romstage.c
M src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c
M src/mainboard/supermicro/h8qme_fam10/romstage.c
M src/mainboard/supermicro/h8scm_fam10/romstage.c
M src/mainboard/tyan/s2912_fam10/get_bus_conf.c
M src/mainboard/tyan/s2912_fam10/romstage.c
M src/mainboard/via/epia-m850/mainboard.c
M src/northbridge/amd/agesa/family12/northbridge.c
M src/northbridge/amd/agesa/family14/northbridge.c
M src/northbridge/amd/agesa/family15tn/northbridge.c
M src/northbridge/amd/agesa/family16kb/northbridge.c
M src/northbridge/amd/agesa/family16kb/state_machine.c
M src/northbridge/amd/agesa/state_machine.h
M src/northbridge/amd/amdfam10/debug.c
M src/northbridge/amd/amdfam10/debug.h
M src/northbridge/amd/amdfam10/early_ht.c
M src/northbridge/amd/amdfam10/link_control.c
M src/northbridge/amd/amdfam10/misc_control.c
M src/northbridge/amd/amdfam10/northbridge.c
M src/northbridge/amd/amdfam10/raminit_amdmct.c
M src/northbridge/amd/amdht/h3finit.c
M src/northbridge/amd/amdht/ht_wrapper.c
M src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
M src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
M src/northbridge/amd/amdmct/wrappers/mcti.h
M src/northbridge/amd/amdmct/wrappers/mcti_d.c
M src/northbridge/amd/pi/00630F01/northbridge.c
M src/northbridge/amd/pi/00660F01/northbridge.c
M src/northbridge/amd/pi/00730F01/northbridge.c
M src/northbridge/amd/pi/agesawrapper.c
M src/northbridge/amd/pi/agesawrapper.h
M src/northbridge/intel/e7505/raminit.c
M src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c
M src/northbridge/intel/gm45/gma.c
M src/northbridge/intel/haswell/acpi/haswell.asl
M src/northbridge/intel/haswell/gma.c
M src/northbridge/intel/haswell/northbridge.c
M src/northbridge/intel/i440bx/raminit.c
M src/northbridge/intel/i440bx/raminit.h
M src/northbridge/intel/i945/early_init.c
M src/northbridge/intel/i945/gma.c
M src/northbridge/intel/i945/raminit.c
M src/northbridge/intel/i945/raminit.h
M src/northbridge/intel/nehalem/acpi/nehalem.asl
M src/northbridge/intel/nehalem/early_init.c
M src/northbridge/intel/nehalem/gma.c
M src/northbridge/intel/nehalem/northbridge.c
M src/northbridge/intel/pineview/gma.c
M src/northbridge/intel/pineview/raminit.c
M src/northbridge/intel/sandybridge/acpi/sandybridge.asl
M src/northbridge/intel/sandybridge/early_init.c
M src/northbridge/intel/sandybridge/gma.c
M src/northbridge/intel/sandybridge/northbridge.c
M src/northbridge/intel/sandybridge/pcie.c
M src/northbridge/intel/sandybridge/raminit.c
M src/northbridge/intel/sandybridge/raminit_common.c
M src/northbridge/intel/sandybridge/raminit_mrc.c
M src/northbridge/intel/x4x/early_init.c
M src/northbridge/intel/x4x/gma.c
M src/northbridge/intel/x4x/raminit.c
M src/northbridge/intel/x4x/raminit_ddr23.c
M src/northbridge/via/vx900/lpc.c
M src/security/tpm/tspi/tspi.c
M src/security/tpm/tss.h
M src/security/vboot/bootmode.c
M src/security/vboot/common.c
M src/security/vboot/secdata_tpm.c
M src/security/vboot/vbnv.c
M src/security/vboot/vbnv_cmos.c
M src/security/vboot/vboot_common.c
M src/security/vboot/vboot_common.h
M src/security/vboot/vboot_crtm.c
M src/security/vboot/vboot_crtm.h
M src/security/vboot/vboot_handoff.c
M src/security/vboot/vboot_loader.c
M src/security/vboot/vboot_logic.c
M src/security/vboot/verstage.c
M src/soc/amd/common/block/pi/refcode_loader.c
M src/soc/amd/common/block/psp/psp.c
M src/soc/amd/stoneyridge/BiosCallOuts.c
M src/soc/amd/stoneyridge/acpi.c
M src/soc/amd/stoneyridge/acpi/sleepstates.asl
M src/soc/amd/stoneyridge/bootblock/bootblock.c
M src/soc/amd/stoneyridge/chip.c
M src/soc/amd/stoneyridge/finalize.c
M src/soc/amd/stoneyridge/include/soc/acpi.h
M src/soc/amd/stoneyridge/include/soc/iomap.h
M src/soc/amd/stoneyridge/lpc.c
M src/soc/amd/stoneyridge/mca.c
M src/soc/amd/stoneyridge/northbridge.c
M src/soc/amd/stoneyridge/ramtop.c
M src/soc/amd/stoneyridge/romstage.c
M src/soc/amd/stoneyridge/smihandler.c
M src/soc/amd/stoneyridge/southbridge.c
M src/soc/amd/stoneyridge/spi.c
M src/soc/cavium/cn81xx/soc.c
M src/soc/cavium/common/bootblock.c
M src/soc/intel/apollolake/acpi.c
M src/soc/intel/apollolake/acpi/pci_irqs.asl
M src/soc/intel/apollolake/acpi/southbridge.asl
M src/soc/intel/apollolake/acpi/xhci.asl
M src/soc/intel/apollolake/bootblock/bootblock.c
M src/soc/intel/apollolake/chip.c
M src/soc/intel/apollolake/cpu.c
M src/soc/intel/apollolake/cse.c
M src/soc/intel/apollolake/graphics.c
M src/soc/intel/apollolake/include/soc/gpio.h
M src/soc/intel/apollolake/include/soc/pcr_ids.h
M src/soc/intel/apollolake/include/soc/pm.h
M src/soc/intel/apollolake/lpc.c
M src/soc/intel/apollolake/meminit.c
M src/soc/intel/apollolake/memmap.c
M src/soc/intel/apollolake/romstage.c
M src/soc/intel/apollolake/smihandler.c
M src/soc/intel/apollolake/uart.c
M src/soc/intel/baytrail/acpi.c
M src/soc/intel/baytrail/include/soc/pmc.h
M src/soc/intel/baytrail/include/soc/ramstage.h
M src/soc/intel/baytrail/include/soc/romstage.h
M src/soc/intel/baytrail/northcluster.c
M src/soc/intel/baytrail/romstage/raminit.c
M src/soc/intel/baytrail/romstage/romstage.c
M src/soc/intel/baytrail/smihandler.c
M src/soc/intel/baytrail/spi.c
M src/soc/intel/braswell/acpi.c
M src/soc/intel/braswell/acpi/lpc.asl
M src/soc/intel/braswell/gfx.c
M src/soc/intel/braswell/include/soc/pm.h
M src/soc/intel/braswell/memmap.c
M src/soc/intel/braswell/northcluster.c
M src/soc/intel/braswell/romstage/romstage.c
M src/soc/intel/braswell/smihandler.c
M src/soc/intel/braswell/spi.c
M src/soc/intel/broadwell/acpi.c
M src/soc/intel/broadwell/chip.c
M src/soc/intel/broadwell/finalize.c
M src/soc/intel/broadwell/igd.c
M src/soc/intel/broadwell/include/soc/ramstage.h
M src/soc/intel/broadwell/lpc.c
M src/soc/intel/broadwell/me.c
M src/soc/intel/broadwell/pcie.c
M src/soc/intel/broadwell/romstage/power_state.c
M src/soc/intel/broadwell/romstage/raminit.c
M src/soc/intel/broadwell/romstage/romstage.c
M src/soc/intel/broadwell/serialio.c
M src/soc/intel/broadwell/smihandler.c
M src/soc/intel/broadwell/spi.c
M src/soc/intel/broadwell/systemagent.c
M src/soc/intel/cannonlake/acpi.c
M src/soc/intel/cannonlake/acpi/scs.asl
M src/soc/intel/cannonlake/acpi/southbridge.asl
M src/soc/intel/cannonlake/bootblock/bootblock.c
M src/soc/intel/cannonlake/bootblock/cpu.c
M src/soc/intel/cannonlake/bootblock/pch.c
M src/soc/intel/cannonlake/chip.c
M src/soc/intel/cannonlake/chip.h
M src/soc/intel/cannonlake/cnl_memcfg_init.c
M src/soc/intel/cannonlake/cpu.c
M src/soc/intel/cannonlake/fsp_params.c
M src/soc/intel/cannonlake/graphics.c
M src/soc/intel/cannonlake/include/soc/gpio.h
M src/soc/intel/cannonlake/include/soc/pmc.h
M src/soc/intel/cannonlake/include/soc/smm.h
M src/soc/intel/cannonlake/lpc.c
M src/soc/intel/cannonlake/memmap.c
M src/soc/intel/cannonlake/romstage/fsp_params.c
M src/soc/intel/cannonlake/smihandler.c
M src/soc/intel/common/acpi/acpi_debug.asl
M src/soc/intel/common/acpi/platform.asl
M src/soc/intel/common/block/acpi/acpi.c
M src/soc/intel/common/block/cpu/car/cache_as_ram.S
M src/soc/intel/common/block/cpu/car/exit_car.S
M src/soc/intel/common/block/fast_spi/fast_spi.c
M src/soc/intel/common/block/gpio/gpio.c
M src/soc/intel/common/block/gspi/gspi.c
M src/soc/intel/common/block/hda/hda.c
M src/soc/intel/common/block/include/intelblocks/gpio_defs.h
M src/soc/intel/common/block/lpc/lpc_lib.c
M src/soc/intel/common/block/pcie/pcie.c
M src/soc/intel/common/block/pcr/pcr.c
M src/soc/intel/common/block/pmc/pmc.c
M src/soc/intel/common/block/pmc/pmclib.c
M src/soc/intel/common/block/rtc/rtc.c
M src/soc/intel/common/block/sata/sata.c
M src/soc/intel/common/block/scs/sd.c
M src/soc/intel/common/block/smbus/tco.c
M src/soc/intel/common/block/smm/smihandler.c
M src/soc/intel/common/block/smm/smm.c
M src/soc/intel/common/block/spi/spi.c
M src/soc/intel/common/block/systemagent/systemagent.c
M src/soc/intel/common/block/uart/uart.c
M src/soc/intel/common/block/xhci/xhci.c
M src/soc/intel/common/pch/lockdown/lockdown.c
M src/soc/intel/common/vbt.c
M src/soc/intel/denverton_ns/acpi.c
M src/soc/intel/denverton_ns/bootblock/bootblock.c
M src/soc/intel/denverton_ns/bootblock/uart.c
M src/soc/intel/denverton_ns/chip.c
M src/soc/intel/denverton_ns/hob_mem.c
M src/soc/intel/denverton_ns/include/soc/pmc.h
M src/soc/intel/denverton_ns/lpc.c
M src/soc/intel/denverton_ns/memmap.c
M src/soc/intel/denverton_ns/pmc.c
M src/soc/intel/denverton_ns/romstage.c
M src/soc/intel/denverton_ns/smihandler.c
M src/soc/intel/denverton_ns/uart.c
M src/soc/intel/fsp_baytrail/acpi.c
M src/soc/intel/fsp_baytrail/acpi/sleepstates.asl
M src/soc/intel/fsp_baytrail/cpu.c
M src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c
M src/soc/intel/fsp_baytrail/gpio.c
M src/soc/intel/fsp_baytrail/include/soc/pmc.h
M src/soc/intel/fsp_baytrail/include/soc/romstage.h
M src/soc/intel/fsp_baytrail/romstage/romstage.c
M src/soc/intel/fsp_baytrail/smihandler.c
M src/soc/intel/fsp_baytrail/southcluster.c
M src/soc/intel/fsp_baytrail/spi.c
M src/soc/intel/fsp_broadwell_de/chip.c
M src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c
M src/soc/intel/fsp_broadwell_de/romstage/romstage.c
M src/soc/intel/fsp_broadwell_de/southcluster.c
M src/soc/intel/icelake/acpi.c
M src/soc/intel/icelake/bootblock/bootblock.c
M src/soc/intel/icelake/bootblock/cpu.c
M src/soc/intel/icelake/bootblock/pch.c
M src/soc/intel/icelake/chip.c
M src/soc/intel/icelake/graphics.c
M src/soc/intel/icelake/include/soc/smm.h
M src/soc/intel/icelake/lpc.c
M src/soc/intel/icelake/memmap.c
M src/soc/intel/icelake/smihandler.c
M src/soc/intel/quark/bootblock/bootblock.c
M src/soc/intel/quark/bootblock/esram_init.S
M src/soc/intel/quark/i2c.c
M src/soc/intel/quark/romstage/car.c
M src/soc/intel/quark/romstage/car_stage_entry.S
M src/soc/intel/quark/romstage/fsp2_0.c
M src/soc/intel/quark/sd.c
M src/soc/intel/quark/storage_test.c
M src/soc/intel/skylake/acpi.c
M src/soc/intel/skylake/acpi/gpio.asl
M src/soc/intel/skylake/acpi/pch.asl
M src/soc/intel/skylake/acpi/scs.asl
M src/soc/intel/skylake/bootblock/bootblock.c
M src/soc/intel/skylake/bootblock/pch.c
M src/soc/intel/skylake/chip.c
M src/soc/intel/skylake/chip_fsp20.c
M src/soc/intel/skylake/cpu.c
M src/soc/intel/skylake/gpio.c
M src/soc/intel/skylake/graphics.c
M src/soc/intel/skylake/include/soc/bootblock.h
M src/soc/intel/skylake/include/soc/gpio_defs.h
M src/soc/intel/skylake/include/soc/pm.h
M src/soc/intel/skylake/include/soc/smm.h
M src/soc/intel/skylake/include/soc/vr_config.h
M src/soc/intel/skylake/me.c
M src/soc/intel/skylake/memmap.c
M src/soc/intel/skylake/romstage/car_stage.S
M src/soc/intel/skylake/romstage/romstage.c
M src/soc/intel/skylake/romstage/romstage_fsp20.c
M src/soc/intel/skylake/smihandler.c
M src/soc/intel/skylake/vr_config.c
M src/soc/mediatek/mt8173/i2c.c
M src/soc/mediatek/mt8173/include/soc/dramc_pi_api.h
M src/soc/mediatek/mt8173/memory.c
M src/soc/mediatek/mt8173/mt6391.c
M src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h
M src/soc/mediatek/mt8183/memory.c
M src/soc/nvidia/tegra210/ccplex.c
M src/soc/nvidia/tegra210/include/soc/console_uart.h
M src/soc/nvidia/tegra210/include/soc/mtc.h
M src/soc/nvidia/tegra210/romstage.c
M src/soc/nvidia/tegra210/soc.c
M src/soc/qualcomm/ipq40xx/uart.c
M src/soc/rockchip/common/gpio.c
M src/soc/rockchip/common/pwm.c
M src/soc/rockchip/rk3399/clock.c
M src/soc/rockchip/rk3399/soc.c
M src/southbridge/amd/agesa/hudson/acpi/fch.asl
M src/southbridge/amd/agesa/hudson/acpi/usb.asl
M src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h
M src/southbridge/amd/agesa/hudson/amd_pci_int_types.h
M src/southbridge/amd/agesa/hudson/fadt.c
M src/southbridge/amd/agesa/hudson/hudson.c
M src/southbridge/amd/agesa/hudson/imc.c
M src/southbridge/amd/agesa/hudson/lpc.c
M src/southbridge/amd/agesa/hudson/pci_devs.h
M src/southbridge/amd/agesa/hudson/resume.c
M src/southbridge/amd/agesa/hudson/sata.c
M src/southbridge/amd/agesa/hudson/spi.c
M src/southbridge/amd/amd8111/acpi.c
M src/southbridge/amd/amd8111/acpi/sleepstates.asl
M src/southbridge/amd/amd8111/lpc.c
M src/southbridge/amd/cimx/sb800/SBPLATFORM.h
M src/southbridge/amd/cimx/sb800/bootblock.c
M src/southbridge/amd/cimx/sb800/late.c
M src/southbridge/amd/cimx/sb800/spi.c
M src/southbridge/amd/cimx/sb900/late.c
M src/southbridge/amd/common/acpi/sleepstates.asl
M src/southbridge/amd/pi/hudson/acpi/fch.asl
M src/southbridge/amd/pi/hudson/acpi/usb.asl
M src/southbridge/amd/pi/hudson/amd_pci_int_defs.h
M src/southbridge/amd/pi/hudson/amd_pci_int_types.h
M src/southbridge/amd/pi/hudson/early_setup.c
M src/southbridge/amd/pi/hudson/fadt.c
M src/southbridge/amd/pi/hudson/gpio.h
M src/southbridge/amd/pi/hudson/hudson.c
M src/southbridge/amd/pi/hudson/hudson.h
M src/southbridge/amd/pi/hudson/lpc.c
M src/southbridge/amd/pi/hudson/pci_devs.h
M src/southbridge/amd/pi/hudson/sata.c
M src/southbridge/amd/rs780/cmn.c
M src/southbridge/amd/rs780/early_setup.c
M src/southbridge/amd/rs780/gfx.c
M src/southbridge/amd/rs780/rs780.c
M src/southbridge/amd/sb700/bootblock.c
M src/southbridge/amd/sb700/early_setup.c
M src/southbridge/amd/sb700/fadt.c
M src/southbridge/amd/sb700/lpc.c
M src/southbridge/amd/sb700/sata.c
M src/southbridge/amd/sb700/sb700.c
M src/southbridge/amd/sb700/sm.c
M src/southbridge/amd/sb700/usb.c
M src/southbridge/amd/sb800/fadt.c
M src/southbridge/amd/sb800/lpc.c
M src/southbridge/amd/sr5650/early_setup.c
M src/southbridge/amd/sr5650/ht.c
M src/southbridge/amd/sr5650/sr5650.c
M src/southbridge/intel/bd82x6x/lpc.c
M src/southbridge/intel/bd82x6x/me.c
M src/southbridge/intel/bd82x6x/me_8.x.c
M src/southbridge/intel/bd82x6x/pch.h
M src/southbridge/intel/bd82x6x/usb_ehci.c
M src/southbridge/intel/common/finalize.c
M src/southbridge/intel/common/pmutil.h
M src/southbridge/intel/common/rtc.c
M src/southbridge/intel/common/smbus.c
M src/southbridge/intel/common/smi.c
M src/southbridge/intel/common/smihandler.c
M src/southbridge/intel/common/spi.c
M src/southbridge/intel/common/usb_debug.c
M src/southbridge/intel/fsp_rangeley/acpi.c
M src/southbridge/intel/fsp_rangeley/lpc.c
M src/southbridge/intel/fsp_rangeley/romstage.c
M src/southbridge/intel/fsp_rangeley/soc.h
M src/southbridge/intel/fsp_rangeley/spi.c
M src/southbridge/intel/i82371eb/isa.c
M src/southbridge/intel/i82801gx/lpc.c
M src/southbridge/intel/i82801ix/acpi/sleepstates.asl
M src/southbridge/intel/i82801ix/i82801ix.c
M src/southbridge/intel/i82801ix/i82801ix.h
M src/southbridge/intel/i82801ix/lpc.c
M src/southbridge/intel/i82801jx/acpi/sleepstates.asl
M src/southbridge/intel/i82801jx/i82801jx.c
M src/southbridge/intel/i82801jx/lpc.c
M src/southbridge/intel/ibexpeak/lpc.c
M src/southbridge/intel/ibexpeak/me.c
M src/southbridge/intel/ibexpeak/pch.h
M src/southbridge/intel/ibexpeak/smi.c
M src/southbridge/intel/ibexpeak/smihandler.c
M src/southbridge/intel/lynxpoint/acpi/pch.asl
M src/southbridge/intel/lynxpoint/early_pch.c
M src/southbridge/intel/lynxpoint/lpc.c
M src/southbridge/intel/lynxpoint/me_9.x.c
M src/southbridge/intel/lynxpoint/pch.h
M src/southbridge/intel/lynxpoint/pmutil.c
M src/southbridge/intel/lynxpoint/smi.c
M src/southbridge/intel/lynxpoint/smihandler.c
M src/southbridge/nvidia/ck804/early_setup_car.c
M src/southbridge/nvidia/ck804/ht.c
M src/southbridge/nvidia/ck804/lpc.c
M src/southbridge/nvidia/mcp55/azalia.c
M src/southbridge/nvidia/mcp55/early_setup_car.c
M src/southbridge/nvidia/mcp55/ht.c
M src/southbridge/nvidia/mcp55/lpc.c
M src/southbridge/nvidia/mcp55/smbus.c
M src/superio/ite/common/env_ctrl.c
M src/superio/ite/common/env_ctrl.h
M src/superio/ite/common/env_ctrl_chip.h
M src/superio/ite/it8716f/superio.c
M src/superio/nuvoton/common/early_serial.c
M src/superio/nuvoton/npcd378/superio.c
M src/superio/via/vt1211/superio.c
M src/vendorcode/amd/agesa/common/agesa-entry-cfg.h
M src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mp.c
M src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc
M src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc
M src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc
M src/vendorcode/cavium/bdk/libdram/libdram.c
M src/vendorcode/cavium/include/bdk/libbdk-arch/bdk-warn.h
M src/vendorcode/google/chromeos/acpi.c
M src/vendorcode/google/chromeos/acpi/chromeos.asl
M src/vendorcode/google/chromeos/chromeos.h
M src/vendorcode/google/chromeos/cr50_enable_update.c
M src/vendorcode/google/chromeos/elog.c
M src/vendorcode/google/chromeos/ramoops.c
M src/vendorcode/google/chromeos/sar.c
M src/vendorcode/google/chromeos/tpm2.c
918 files changed, 2,278 insertions(+), 2,278 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/31774/1

[build bot (Jenkins) (Code Review)]

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31774 )

Change subject: coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)
......................................................................

Patch Set 2:

(28 comments)

https://review.coreboot.org/#/c/31774/2/src/console/printk.c 
File src/console/printk.c:

https://review.coreboot.org/#/c/31774/2/src/console/printk.c@29 
PS2, Line 29: #if (!defined(__PRE_RAM__) && CONFIG(HAVE_ROMSTAGE_CONSOLE_SPINLOCK)) || !CONFIG(HAVE_ROMSTAGE_CONSOLE_SPINLOCK)
line over 96 characters

https://review.coreboot.org/#/c/31774/2/src/cpu/amd/pi/00630F01/fixme.c 
File src/cpu/amd/pi/00630F01/fixme.c:

https://review.coreboot.org/#/c/31774/2/src/cpu/amd/pi/00630F01/fixme.c@91 
PS2, Line 91: 	if (CONFIG(UDELAY_LAPIC)){
space required before the open brace '{'

https://review.coreboot.org/#/c/31774/2/src/device/pci_rom.c 
File src/device/pci_rom.c:

https://review.coreboot.org/#/c/31774/2/src/device/pci_rom.c@58 
PS2, Line 58: 	} else if (!CONFIG(ON_DEVICE_ROM_LOAD)) {
suspect code indent for conditional statements (8, 24)

https://review.coreboot.org/#/c/31774/2/src/drivers/pc80/tpm/tis.c 
File src/drivers/pc80/tpm/tis.c:

https://review.coreboot.org/#/c/31774/2/src/drivers/pc80/tpm/tis.c@129 
PS2, Line 129: #if CONFIG(TPM2)
braces {} are not necessary for single statement blocks

https://review.coreboot.org/#/c/31774/2/src/drivers/spi/spi_flash.c 
File src/drivers/spi/spi_flash.c:

https://review.coreboot.org/#/c/31774/2/src/drivers/spi/spi_flash.c@279 
PS2, Line 279: #if CONFIG(SPI_FLASH_AMIC)
braces {} are not necessary for single statement blocks

https://review.coreboot.org/#/c/31774/2/src/drivers/spi/spi_flash.c@282 
PS2, Line 282: #if CONFIG(SPI_FLASH_ATMEL)
braces {} are not necessary for single statement blocks

https://review.coreboot.org/#/c/31774/2/src/drivers/spi/spi_flash.c@285 
PS2, Line 285: #if CONFIG(SPI_FLASH_EON)
braces {} are not necessary for single statement blocks

https://review.coreboot.org/#/c/31774/2/src/drivers/spi/spi_flash.c@288 
PS2, Line 288: #if CONFIG(SPI_FLASH_GIGADEVICE)
braces {} are not necessary for single statement blocks

https://review.coreboot.org/#/c/31774/2/src/drivers/spi/spi_flash.c@291 
PS2, Line 291: #if CONFIG(SPI_FLASH_MACRONIX)
braces {} are not necessary for single statement blocks

https://review.coreboot.org/#/c/31774/2/src/drivers/spi/spi_flash.c@294 
PS2, Line 294: #if CONFIG(SPI_FLASH_SPANSION)
braces {} are not necessary for single statement blocks

https://review.coreboot.org/#/c/31774/2/src/drivers/spi/spi_flash.c@297 
PS2, Line 297: #if CONFIG(SPI_FLASH_SST)
braces {} are not necessary for single statement blocks

https://review.coreboot.org/#/c/31774/2/src/drivers/spi/spi_flash.c@300 
PS2, Line 300: #if CONFIG(SPI_FLASH_STMICRO)
braces {} are not necessary for single statement blocks

https://review.coreboot.org/#/c/31774/2/src/drivers/spi/spi_flash.c@303 
PS2, Line 303: #if CONFIG(SPI_FLASH_WINBOND)
braces {} are not necessary for single statement blocks

https://review.coreboot.org/#/c/31774/2/src/drivers/spi/spi_flash.c@307 
PS2, Line 307: #if CONFIG(SPI_FLASH_STMICRO)
braces {} are not necessary for single statement blocks

https://review.coreboot.org/#/c/31774/2/src/drivers/spi/spi_flash.c@310 
PS2, Line 310: #if CONFIG(SPI_FLASH_ADESTO)
braces {} are not necessary for single statement blocks

https://review.coreboot.org/#/c/31774/2/src/lib/prog_loaders.c 
File src/lib/prog_loaders.c:

https://review.coreboot.org/#/c/31774/2/src/lib/prog_loaders.c@84 
PS2, Line 84: 	if (CONFIG(RESET_ON_INVALID_RAMSTAGE_CACHE)) {
braces {} are not necessary for single statement blocks

https://review.coreboot.org/#/c/31774/2/src/mainboard/amd/lamar/OemCustomize... 
File src/mainboard/amd/lamar/OemCustomize.c:

https://review.coreboot.org/#/c/31774/2/src/mainboard/amd/lamar/OemCustomize... 
PS2, Line 61: 				CONFIG(ENABLE_DP3_DAUGHTER_CARD_IN_J120) ? PcieUnusedEngine : PciePortEngine,
line over 96 characters

https://review.coreboot.org/#/c/31774/2/src/mainboard/amd/lamar/OemCustomize... 
PS2, Line 81: 				CONFIG(ENABLE_DP3_DAUGHTER_CARD_IN_J120) ? PcieDdiEngine : PcieUnusedEngine,
line over 96 characters

https://review.coreboot.org/#/c/31774/2/src/mainboard/emulation/qemu-power8/... 
File src/mainboard/emulation/qemu-power8/bootblock.c:

https://review.coreboot.org/#/c/31774/2/src/mainboard/emulation/qemu-power8/... 
PS2, Line 25: 	if (CONFIG(BOOTBLOCK_CONSOLE)) {
braces {} are not necessary for single statement blocks

https://review.coreboot.org/#/c/31774/2/src/mainboard/google/gru/chromeos.c 
File src/mainboard/google/gru/chromeos.c:

https://review.coreboot.org/#/c/31774/2/src/mainboard/google/gru/chromeos.c@... 
PS2, Line 39: #if CONFIG(GRU_BASEBOARD_SCARLET)
braces {} are not necessary for single statement blocks

https://review.coreboot.org/#/c/31774/2/src/mainboard/google/gru/chromeos.c@... 
PS2, Line 46: #if CONFIG(GRU_HAS_TPM2)
braces {} are not necessary for single statement blocks

https://review.coreboot.org/#/c/31774/2/src/mainboard/google/jecht/smihandle... 
File src/mainboard/google/jecht/smihandler.c:

https://review.coreboot.org/#/c/31774/2/src/mainboard/google/jecht/smihandle... 
PS2, Line 62: 		if (CONFIG(BOARD_GOOGLE_TIDUS)) {
braces {} are not necessary for single statement blocks

https://review.coreboot.org/#/c/31774/2/src/mainboard/pcengines/apu2/romstag... 
File src/mainboard/pcengines/apu2/romstage.c:

https://review.coreboot.org/#/c/31774/2/src/mainboard/pcengines/apu2/romstag... 
PS2, Line 146: 	if (CONFIG(BOARD_PCENGINES_APU5)) {
braces {} are not necessary for single statement blocks

https://review.coreboot.org/#/c/31774/2/src/northbridge/intel/haswell/gma.c 
File src/northbridge/intel/haswell/gma.c:

https://review.coreboot.org/#/c/31774/2/src/northbridge/intel/haswell/gma.c@... 
PS2, Line 243: 	if (CONFIG(MAINBOARD_DO_NATIVE_VGA_INIT)) {
braces {} are not necessary for single statement blocks

https://review.coreboot.org/#/c/31774/2/src/soc/intel/cannonlake/acpi.c 
File src/soc/intel/cannonlake/acpi.c:

https://review.coreboot.org/#/c/31774/2/src/soc/intel/cannonlake/acpi.c@207 
PS2, Line 207: 	if (CONFIG(CONSOLE_CBMEM))
suspect code indent for conditional statements (8, 8)

https://review.coreboot.org/#/c/31774/2/src/soc/intel/quark/storage_test.c 
File src/soc/intel/quark/storage_test.c:

https://review.coreboot.org/#/c/31774/2/src/soc/intel/quark/storage_test.c@1... 
PS2, Line 136: 	if (CONFIG(STORAGE_LOG)) {
braces {} are not necessary for single statement blocks

https://review.coreboot.org/#/c/31774/2/src/soc/intel/skylake/gpio.c 
File src/soc/intel/skylake/gpio.c:

https://review.coreboot.org/#/c/31774/2/src/soc/intel/skylake/gpio.c@162 
PS2, Line 162: #if CONFIG(SKYLAKE_SOC_PCH_H)
braces {} are not necessary for single statement blocks

https://review.coreboot.org/#/c/31774/2/src/southbridge/amd/sb700/sm.c 
File src/southbridge/amd/sb700/sm.c:

https://review.coreboot.org/#/c/31774/2/src/southbridge/amd/sb700/sm.c@308 
PS2, Line 308: 	if (CONFIG(ENABLE_APIC_EXT_ID))
suspect code indent for conditional statements (8, 8)

[Julius Werner (Code Review)]

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31774 )

Change subject: coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)
......................................................................

Patch Set 2:

What about this one, Patrick? Probably better to land them at the same time? (Note that all the Jenkins warnings, while valid, are in existing code so I don't plan to fix them for this refactoring.)

[Martin Roth (Code Review)]

Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31774 )

Change subject: coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)
......................................................................

Patch Set 2: Code-Review+2

Needs to be updated - it doesn't merge cleanly on the tree anymore.
I'm going to +2, but I admit I haven't gone through and verified that Julius didn't stick some nefarious code changes into the commit.  :)

Julius, if Patrick doesn't handle this tonight, I'll be glad to work with you to get it in tomorrow.

[Julius Werner (Code Review)]

Hello Patrick Rudolph, Aaron Durbin, Piotr Król, Angel Pons, Patrick Rudolph, build bot (Jenkins), Philipp Hug, Patrick Georgi, Alexander Couzens, Werner Zeh, ron minnich, Felix Held, Vanessa Eusebio, Huang Jin, York Yang, Lee Leahy, Jonathan Neuschäfer, Philipp Deppenwiese, Martin Roth, David Guckian, Michał Żygowski, Damien Zammit,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/31774

to look at the new patch set (#3).

Change subject: coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)
......................................................................

coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)

This patch is a raw application of

find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'

Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner 
---
M src/arch/arm/armv7/mmu.c
M src/arch/arm/include/arch/memlayout.h
M src/arch/arm/include/armv7/arch/cache.h
M src/arch/arm/tables.c
M src/arch/arm64/arm_tf.c
M src/arch/arm64/armv8/exception.c
M src/arch/arm64/boot.c
M src/arch/arm64/include/armv8/arch/barrier.h
M src/arch/arm64/tables.c
M src/arch/mips/bootblock_simple.c
M src/arch/ppc64/include/arch/cpu.h
M src/arch/riscv/include/arch/cpu.h
M src/arch/riscv/sbi.c
M src/arch/x86/acpi.c
M src/arch/x86/acpi_device.c
M src/arch/x86/acpi_s3.c
M src/arch/x86/assembly_entry.S
M src/arch/x86/bootblock.ld
M src/arch/x86/bootblock_crt0.S
M src/arch/x86/bootblock_romcc.S
M src/arch/x86/bootblock_simple.c
M src/arch/x86/c_start.S
M src/arch/x86/car.ld
M src/arch/x86/cbmem.c
M src/arch/x86/cpu.c
M src/arch/x86/exception.c
M src/arch/x86/exit_car.S
M src/arch/x86/gdt.c
M src/arch/x86/include/arch/acpi.h
M src/arch/x86/include/arch/cpu.h
M src/arch/x86/include/arch/early_variables.h
M src/arch/x86/include/arch/exception.h
M src/arch/x86/include/arch/interrupt.h
M src/arch/x86/include/arch/pci_io_cfg.h
M src/arch/x86/include/arch/registers.h
M src/arch/x86/include/arch/smp/spinlock.h
M src/arch/x86/include/cf9_reset.h
M src/arch/x86/ioapic.c
M src/arch/x86/memlayout.ld
M src/arch/x86/pci_ops_conf1.c
M src/arch/x86/pirq_routing.c
M src/arch/x86/postcar_loader.c
M src/arch/x86/smbios.c
M src/arch/x86/tables.c
M src/arch/x86/timestamp.c
M src/commonlib/cbfs.c
M src/commonlib/include/commonlib/stdlib.h
M src/commonlib/storage/mmc.c
M src/commonlib/storage/sd_mmc.c
M src/commonlib/storage/sd_mmc.h
M src/commonlib/storage/sdhci.c
M src/commonlib/storage/sdhci_display.c
M src/commonlib/storage/storage.c
M src/console/console.c
M src/console/init.c
M src/console/post.c
M src/console/printk.c
M src/console/vtxprintf.c
M src/cpu/amd/agesa/family12/model_12_init.c
M src/cpu/amd/agesa/family14/model_14_init.c
M src/cpu/amd/agesa/family15tn/model_15_init.c
M src/cpu/amd/agesa/family16kb/model_16_init.c
M src/cpu/amd/car/cache_as_ram.inc
M src/cpu/amd/car/disable_cache_as_ram.c
M src/cpu/amd/car/post_cache_as_ram.c
M src/cpu/amd/family_10h-family_15h/fidvid.c
M src/cpu/amd/family_10h-family_15h/init_cpus.c
M src/cpu/amd/family_10h-family_15h/model_10xxx_init.c
M src/cpu/amd/family_10h-family_15h/powernow_acpi.c
M src/cpu/amd/family_10h-family_15h/ram_calc.c
M src/cpu/amd/microcode/microcode.c
M src/cpu/amd/pi/00630F01/fixme.c
M src/cpu/amd/pi/00630F01/model_15_init.c
M src/cpu/amd/pi/00660F01/fixme.c
M src/cpu/amd/pi/00660F01/model_15_init.c
M src/cpu/amd/pi/00730F01/fixme.c
M src/cpu/amd/pi/00730F01/model_16_init.c
M src/cpu/amd/quadcore/quadcore.c
M src/cpu/intel/car/non-evict/cache_as_ram.S
M src/cpu/intel/car/p4-netburst/cache_as_ram.S
M src/cpu/intel/car/romstage.c
M src/cpu/intel/common/common_init.c
M src/cpu/intel/fsp_model_406dx/model_406dx_init.c
M src/cpu/intel/haswell/bootblock.c
M src/cpu/intel/haswell/romstage.c
M src/cpu/intel/hyperthreading/intel_sibling.c
M src/cpu/intel/model_1067x/mp_init.c
M src/cpu/intel/model_2065x/bootblock.c
M src/cpu/intel/model_206ax/bootblock.c
M src/cpu/intel/model_f3x/model_f3x_init.c
M src/cpu/intel/smm/gen1/smmrelocate.c
M src/cpu/intel/turbo/turbo.c
M src/cpu/x86/16bit/entry16.inc
M src/cpu/x86/32bit/entry32.inc
M src/cpu/x86/backup_default_smm.c
M src/cpu/x86/car.c
M src/cpu/x86/lapic/apic_timer.c
M src/cpu/x86/lapic/boot_cpu.c
M src/cpu/x86/lapic/lapic_cpu_init.c
M src/cpu/x86/mp_init.c
M src/cpu/x86/mtrr/debug.c
M src/cpu/x86/mtrr/mtrr.c
M src/cpu/x86/sipi_vector.S
M src/cpu/x86/smm/smihandler.c
M src/cpu/x86/smm/smm_module_handler.c
M src/cpu/x86/smm/smm_module_loader.c
M src/cpu/x86/smm/smmhandler.S
M src/cpu/x86/smm/smmrelocate.S
M src/cpu/x86/tsc/delay_tsc.c
M src/device/device.c
M src/device/device_const.c
M src/device/oprom/include/io.h
M src/device/oprom/include/x86emu/fpu_regs.h
M src/device/oprom/include/x86emu/regs.h
M src/device/oprom/include/x86emu/x86emu.h
M src/device/oprom/realmode/x86.c
M src/device/oprom/realmode/x86_interrupts.c
M src/device/oprom/yabel/biosemu.c
M src/device/oprom/yabel/compat/functions.c
M src/device/oprom/yabel/debug.h
M src/device/oprom/yabel/device.c
M src/device/oprom/yabel/device.h
M src/device/oprom/yabel/interrupt.c
M src/device/oprom/yabel/io.c
M src/device/oprom/yabel/mem.c
M src/device/oprom/yabel/vbe.c
M src/device/pci_device.c
M src/device/pci_rom.c
M src/device/pciexp_device.c
M src/device/root_device.c
M src/drivers/amd/agesa/acpi_tables.c
M src/drivers/amd/agesa/cache_as_ram.S
M src/drivers/amd/agesa/def_callouts.c
M src/drivers/amd/agesa/eventlog.c
M src/drivers/amd/agesa/heapmanager.c
M src/drivers/amd/agesa/oem_s3.c
M src/drivers/amd/agesa/romstage.c
M src/drivers/amd/agesa/state_machine.c
M src/drivers/elog/boot_count.c
M src/drivers/elog/elog.c
M src/drivers/emulation/qemu/bochs.c
M src/drivers/emulation/qemu/cirrus.c
M src/drivers/generic/adau7002/adau7002.c
M src/drivers/generic/generic/chip.h
M src/drivers/generic/max98357a/max98357a.c
M src/drivers/i2c/da7219/da7219.c
M src/drivers/i2c/designware/dw_i2c.c
M src/drivers/i2c/designware/dw_i2c.h
M src/drivers/i2c/generic/generic.c
M src/drivers/i2c/hid/hid.c
M src/drivers/i2c/nau8825/nau8825.c
M src/drivers/i2c/tpm/tis.c
M src/drivers/i2c/tpm/tis_atmel.c
M src/drivers/i2c/w83795/w83795.c
M src/drivers/intel/fsp1_0/cache_as_ram.inc
M src/drivers/intel/fsp1_0/fastboot_cache.c
M src/drivers/intel/fsp1_0/fsp_util.c
M src/drivers/intel/fsp1_0/fsp_util.h
M src/drivers/intel/fsp1_1/after_raminit.S
M src/drivers/intel/fsp1_1/cache_as_ram.inc
M src/drivers/intel/fsp1_1/fsp_util.c
M src/drivers/intel/fsp1_1/raminit.c
M src/drivers/intel/fsp1_1/ramstage.c
M src/drivers/intel/fsp1_1/romstage.c
M src/drivers/intel/fsp1_1/stack.c
M src/drivers/intel/fsp1_1/vbt.c
M src/drivers/intel/fsp2_0/debug.c
M src/drivers/intel/fsp2_0/hand_off_block.c
M src/drivers/intel/fsp2_0/include/fsp/soc_binding.h
M src/drivers/intel/fsp2_0/memory_init.c
M src/drivers/intel/fsp2_0/silicon_init.c
M src/drivers/intel/fsp2_0/util.c
M src/drivers/intel/gma/int15.h
M src/drivers/intel/gma/opregion.c
M src/drivers/intel/gma/vbt.c
M src/drivers/intel/wifi/wifi.c
M src/drivers/lenovo/wacom.c
M src/drivers/mrc_cache/mrc_cache.c
M src/drivers/net/r8168.c
M src/drivers/pc80/pc/i8254.c
M src/drivers/pc80/rtc/mc146818rtc.c
M src/drivers/pc80/rtc/mc146818rtc_boot.c
M src/drivers/pc80/rtc/mc146818rtc_romcc.c
M src/drivers/pc80/tpm/tis.c
M src/drivers/siemens/nc_fpga/nc_fpga.c
M src/drivers/smmstore/store.c
M src/drivers/spi/adesto.c
M src/drivers/spi/amic.c
M src/drivers/spi/atmel.c
M src/drivers/spi/eon.c
M src/drivers/spi/gigadevice.c
M src/drivers/spi/macronix.c
M src/drivers/spi/spansion.c
M src/drivers/spi/spi_flash.c
M src/drivers/spi/sst.c
M src/drivers/spi/stmicro.c
M src/drivers/spi/winbond.c
M src/drivers/tpm/tpm.c
M src/drivers/uart/uart8250io.c
M src/drivers/uart/uart8250mem.c
M src/drivers/uart/util.c
M src/drivers/usb/ehci_debug.c
M src/drivers/usb/gadget.c
M src/drivers/xgi/common/vb_init.c
M src/drivers/xgi/common/xgi_coreboot.c
M src/drivers/xgi/z9s/z9s.c
M src/ec/google/chromeec/acpi/ec.asl
M src/ec/google/chromeec/ec.c
M src/ec/google/chromeec/ec_i2c.c
M src/ec/google/chromeec/ec_lpc.c
M src/ec/google/chromeec/smihandler.c
M src/ec/google/chromeec/switches.c
M src/ec/google/wilco/acpi/superio.asl
M src/ec/google/wilco/bootblock.c
M src/ec/kontron/kempld/early_kempld.c
M src/ec/lenovo/h8/acpi/thinkpad.asl
M src/ec/lenovo/h8/h8.c
M src/ec/lenovo/h8/panic.c
M src/ec/quanta/ene_kb3940q/ec.c
M src/include/adainit.h
M src/include/assert.h
M src/include/bootstate.h
M src/include/cbmem.h
M src/include/console/cbmem_console.h
M src/include/console/console.h
M src/include/console/flash.h
M src/include/console/ne2k.h
M src/include/console/qemu_debugcon.h
M src/include/console/spi.h
M src/include/console/spkmodem.h
M src/include/console/uart.h
M src/include/console/usb.h
M src/include/cper.h
M src/include/cpu/x86/lapic.h
M src/include/cpu/x86/msr.h
M src/include/cpu/x86/post_code.h
M src/include/cpu/x86/smm.h
M src/include/cpu/x86/tsc.h
M src/include/device/device.h
M src/include/device/dram/common.h
M src/include/device/dram/ddr3.h
M src/include/device/early_smbus.h
M src/include/device/pci.h
M src/include/device/pci_ehci.h
M src/include/device/pci_mmio_cfg.h
M src/include/device/smbus.h
M src/include/elog.h
M src/include/gic.h
M src/include/memlayout.h
M src/include/option.h
M src/include/pc80/mc146818rtc.h
M src/include/reg_script.h
M src/include/rmodule.h
M src/include/rules.h
M src/include/smp/atomic.h
M src/include/smp/node.h
M src/include/smp/spinlock.h
M src/include/stddef.h
M src/include/thread.h
M src/include/timer.h
M src/include/timestamp.h
M src/include/trace.h
M src/include/watchdog.h
M src/lib/bootblock.c
M src/lib/bootmode.c
M src/lib/cbfs.c
M src/lib/cbmem_console.c
M src/lib/coreboot_table.c
M src/lib/decompressor.c
M src/lib/edid.c
M src/lib/fallback_boot.c
M src/lib/gcov-glue.c
M src/lib/hardwaremain.c
M src/lib/imd_cbmem.c
M src/lib/libgcc.c
M src/lib/malloc.c
M src/lib/prog_loaders.c
M src/lib/program.ld
M src/lib/ramtest.c
M src/lib/reg_script.c
M src/lib/reset.c
M src/lib/spd_bin.c
M src/lib/timestamp.c
M src/mainboard/advansus/a785e-i/get_bus_conf.c
M src/mainboard/advansus/a785e-i/romstage.c
M src/mainboard/amd/bettong/BiosCallOuts.c
M src/mainboard/amd/bettong/romstage.c
M src/mainboard/amd/bimini_fam10/get_bus_conf.c
M src/mainboard/amd/bimini_fam10/romstage.c
M src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c
M src/mainboard/amd/lamar/BiosCallOuts.c
M src/mainboard/amd/lamar/OemCustomize.c
M src/mainboard/amd/mahogany_fam10/get_bus_conf.c
M src/mainboard/amd/mahogany_fam10/romstage.c
M src/mainboard/amd/olivehill/BiosCallOuts.c
M src/mainboard/amd/olivehill/OemCustomize.c
M src/mainboard/amd/olivehillplus/BiosCallOuts.c
M src/mainboard/amd/parmer/BiosCallOuts.c
M src/mainboard/amd/parmer/OemCustomize.c
M src/mainboard/amd/parmer/buildOpts.c
M src/mainboard/amd/serengeti_cheetah_fam10/mptable.c
M src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
M src/mainboard/amd/thatcher/BiosCallOuts.c
M src/mainboard/amd/thatcher/buildOpts.c
M src/mainboard/amd/tilapia_fam10/get_bus_conf.c
M src/mainboard/amd/tilapia_fam10/romstage.c
M src/mainboard/amd/torpedo/Oem.h
M src/mainboard/amd/torpedo/platform_cfg.h
M src/mainboard/apple/macbook21/gpio.c
M src/mainboard/apple/macbook21/hda_verb.c
M src/mainboard/asrock/g41c-gs/acpi/ich7_pci_irqs.asl
M src/mainboard/asrock/g41c-gs/romstage.c
M src/mainboard/asrock/imb-a180/OemCustomize.c
M src/mainboard/asus/am1i-a/BiosCallOuts.c
M src/mainboard/asus/am1i-a/OemCustomize.c
M src/mainboard/asus/f2a85-m/BiosCallOuts.c
M src/mainboard/asus/f2a85-m/OemCustomize.c
M src/mainboard/asus/f2a85-m/acpi/routing.asl
M src/mainboard/asus/f2a85-m/buildOpts.c
M src/mainboard/asus/f2a85-m/romstage.c
M src/mainboard/asus/kcma-d8/acpi_tables.c
M src/mainboard/asus/kcma-d8/bootblock.c
M src/mainboard/asus/kcma-d8/mptable.c
M src/mainboard/asus/kcma-d8/romstage.c
M src/mainboard/asus/kfsn4-dre/acpi_tables.c
M src/mainboard/asus/kfsn4-dre/bootblock.c
M src/mainboard/asus/kfsn4-dre/get_bus_conf.c
M src/mainboard/asus/kfsn4-dre/romstage.c
M src/mainboard/asus/kgpe-d16/acpi_tables.c
M src/mainboard/asus/kgpe-d16/bootblock.c
M src/mainboard/asus/kgpe-d16/mptable.c
M src/mainboard/asus/kgpe-d16/romstage.c
M src/mainboard/asus/m4a78-em/get_bus_conf.c
M src/mainboard/asus/m4a78-em/romstage.c
M src/mainboard/asus/m4a785-m/get_bus_conf.c
M src/mainboard/asus/m4a785-m/romstage.c
M src/mainboard/asus/m5a88-v/get_bus_conf.c
M src/mainboard/asus/m5a88-v/romstage.c
M src/mainboard/asus/p5qpl-am/romstage.c
M src/mainboard/avalue/eax-785e/get_bus_conf.c
M src/mainboard/avalue/eax-785e/romstage.c
M src/mainboard/bap/ode_e20XX/BiosCallOuts.c
M src/mainboard/bap/ode_e20XX/OemCustomize.c
M src/mainboard/bap/ode_e21XX/BiosCallOuts.c
M src/mainboard/biostar/a68n_5200/BiosCallOuts.c
M src/mainboard/biostar/a68n_5200/OemCustomize.c
M src/mainboard/biostar/a68n_5200/romstage.c
M src/mainboard/biostar/am1ml/BiosCallOuts.c
M src/mainboard/biostar/am1ml/OemCustomize.c
M src/mainboard/cavium/cn8100_sff_evb/bootblock.c
M src/mainboard/compulab/intense_pc/gpio.c
M src/mainboard/compulab/intense_pc/romstage.c
M src/mainboard/emulation/qemu-i440fx/northbridge.c
M src/mainboard/emulation/qemu-power8/bootblock.c
M src/mainboard/foxconn/g41s-k/acpi/superio.asl
M src/mainboard/foxconn/g41s-k/hda_verb.c
M src/mainboard/foxconn/g41s-k/romstage.c
M src/mainboard/gigabyte/ma785gm/get_bus_conf.c
M src/mainboard/gigabyte/ma785gm/romstage.c
M src/mainboard/gigabyte/ma785gmt/get_bus_conf.c
M src/mainboard/gigabyte/ma785gmt/romstage.c
M src/mainboard/gigabyte/ma78gm/get_bus_conf.c
M src/mainboard/gigabyte/ma78gm/romstage.c
M src/mainboard/gizmosphere/gizmo2/BiosCallOuts.c
M src/mainboard/gizmosphere/gizmo2/OemCustomize.c
M src/mainboard/google/auron/acpi/mainboard.asl
M src/mainboard/google/auron/smihandler.c
M src/mainboard/google/auron/variants/buddy/variant.c
M src/mainboard/google/beltino/acpi_tables.c
M src/mainboard/google/beltino/lan.c
M src/mainboard/google/butterfly/mainboard.c
M src/mainboard/google/butterfly/romstage.c
M src/mainboard/google/cyan/acpi/dptf.asl
M src/mainboard/google/cyan/acpi_tables.c
M src/mainboard/google/cyan/chromeos.c
M src/mainboard/google/cyan/dsdt.asl
M src/mainboard/google/cyan/ec.c
M src/mainboard/google/cyan/romstage.c
M src/mainboard/google/cyan/smihandler.c
M src/mainboard/google/cyan/spd/spd.c
M src/mainboard/google/dragonegg/dsdt.asl
M src/mainboard/google/foster/chromeos.c
M src/mainboard/google/gale/mainboard.c
M src/mainboard/google/gale/verstage.c
M src/mainboard/google/glados/mainboard.c
M src/mainboard/google/glados/romstage.c
M src/mainboard/google/glados/smihandler.c
M src/mainboard/google/gru/board.h
M src/mainboard/google/gru/boardid.c
M src/mainboard/google/gru/bootblock.c
M src/mainboard/google/gru/chromeos.c
M src/mainboard/google/gru/mainboard.c
M src/mainboard/google/gru/pwm_regulator.c
M src/mainboard/google/gru/romstage.c
M src/mainboard/google/gru/sdram_configs.c
M src/mainboard/google/hatch/dsdt.asl
M src/mainboard/google/jecht/lan.c
M src/mainboard/google/jecht/led.c
M src/mainboard/google/jecht/romstage.c
M src/mainboard/google/jecht/smihandler.c
M src/mainboard/google/kahlee/OemCustomize.c
M src/mainboard/google/kahlee/bootblock/bootblock.c
M src/mainboard/google/kahlee/smihandler.c
M src/mainboard/google/kahlee/variants/baseboard/mainboard.c
M src/mainboard/google/kukui/boardid.c
M src/mainboard/google/kukui/romstage.c
M src/mainboard/google/link/acpi_tables.c
M src/mainboard/google/link/mainboard.c
M src/mainboard/google/link/mainboard_smi.c
M src/mainboard/google/nyan/romstage.c
M src/mainboard/google/nyan_big/romstage.c
M src/mainboard/google/nyan_blaze/romstage.c
M src/mainboard/google/oak/bootblock.c
M src/mainboard/google/oak/gpio.h
M src/mainboard/google/oak/mainboard.c
M src/mainboard/google/octopus/romstage.c
M src/mainboard/google/octopus/variants/baseboard/memory.c
M src/mainboard/google/octopus/variants/baseboard/nhlt.c
M src/mainboard/google/parrot/acpi_tables.c
M src/mainboard/google/parrot/smihandler.c
M src/mainboard/google/poppy/dsdt.asl
M src/mainboard/google/rambi/mainboard.c
M src/mainboard/google/rambi/mainboard_smi.c
M src/mainboard/google/rambi/variants/ninja/lan.c
M src/mainboard/google/rambi/variants/sumo/lan.c
M src/mainboard/google/reef/smihandler.c
M src/mainboard/google/reef/variants/baseboard/nhlt.c
M src/mainboard/google/reef/variants/snappy/mainboard.c
M src/mainboard/google/sarien/dsdt.asl
M src/mainboard/google/sarien/variants/sarien/ramstage.c
M src/mainboard/google/slippy/acpi_tables.c
M src/mainboard/google/slippy/smihandler.c
M src/mainboard/google/smaug/mainboard.c
M src/mainboard/google/storm/mainboard.c
M src/mainboard/google/stout/acpi_tables.c
M src/mainboard/google/stout/ec.c
M src/mainboard/google/urara/mainboard.c
M src/mainboard/google/veyron/boardid.c
M src/mainboard/google/veyron/bootblock.c
M src/mainboard/google/veyron_mickey/bootblock.c
M src/mainboard/google/veyron_rialto/bootblock.c
M src/mainboard/hp/abm/OemCustomize.c
M src/mainboard/hp/compaq_8200_elite_sff/mainboard.c
M src/mainboard/hp/compaq_8200_elite_sff/romstage.c
M src/mainboard/hp/dl165_g6_fam10/mptable.c
M src/mainboard/hp/dl165_g6_fam10/romstage.c
M src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c
M src/mainboard/hp/pavilion_m6_1035dx/OemCustomize.c
M src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c
M src/mainboard/iei/kino-780am2-fam10/get_bus_conf.c
M src/mainboard/iei/kino-780am2-fam10/romstage.c
M src/mainboard/intel/apollolake_rvp/romstage.c
M src/mainboard/intel/baskingridge/acpi_tables.c
M src/mainboard/intel/bayleybay_fsp/mainboard.c
M src/mainboard/intel/bayleybay_fsp/romstage.c
M src/mainboard/intel/camelbackmountain_fsp/mainboard.c
M src/mainboard/intel/cannonlake_rvp/dsdt.asl
M src/mainboard/intel/cannonlake_rvp/spd/spd_util.c
M src/mainboard/intel/cannonlake_rvp/variants/baseboard/gpio.c
M src/mainboard/intel/cannonlake_rvp/variants/baseboard/nhlt.c
M src/mainboard/intel/coffeelake_rvp/dsdt.asl
M src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c
M src/mainboard/intel/coffeelake_rvp/variants/baseboard/nhlt.c
M src/mainboard/intel/dcp847ske/acpi/superio.asl
M src/mainboard/intel/dcp847ske/early_southbridge.c
M src/mainboard/intel/dcp847ske/romstage.c
M src/mainboard/intel/galileo/gpio.c
M src/mainboard/intel/galileo/mainboard.c
M src/mainboard/intel/galileo/vboot.c
M src/mainboard/intel/glkrvp/boardid.c
M src/mainboard/intel/glkrvp/ec.c
M src/mainboard/intel/glkrvp/romstage.c
M src/mainboard/intel/glkrvp/smihandler.c
M src/mainboard/intel/glkrvp/variants/baseboard/boardid.c
M src/mainboard/intel/glkrvp/variants/baseboard/gpio.c
M src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/gpio.h
M src/mainboard/intel/glkrvp/variants/baseboard/nhlt.c
M src/mainboard/intel/harcuvar/romstage.c
M src/mainboard/intel/icelake_rvp/acpi/mainboard.asl
M src/mainboard/intel/icelake_rvp/board_id.c
M src/mainboard/intel/icelake_rvp/dsdt.asl
M src/mainboard/intel/kblrvp/acpi/ec.asl
M src/mainboard/intel/kblrvp/acpi/mainboard.asl
M src/mainboard/intel/kblrvp/chromeos.c
M src/mainboard/intel/kblrvp/dsdt.asl
M src/mainboard/intel/kblrvp/hda_verb.c
M src/mainboard/intel/kblrvp/mainboard.c
M src/mainboard/intel/kblrvp/ramstage.c
M src/mainboard/intel/kblrvp/romstage.c
M src/mainboard/intel/kblrvp/smihandler.c
M src/mainboard/intel/kunimitsu/smihandler.c
M src/mainboard/intel/strago/ec.c
M src/mainboard/intel/strago/smihandler.c
M src/mainboard/jetway/pa78vm5/get_bus_conf.c
M src/mainboard/jetway/pa78vm5/romstage.c
M src/mainboard/kontron/ktqm77/mainboard.c
M src/mainboard/lenovo/g505s/BiosCallOuts.c
M src/mainboard/lenovo/g505s/OemCustomize.c
M src/mainboard/lenovo/g505s/buildOpts.c
M src/mainboard/lenovo/s230u/romstage.c
M src/mainboard/msi/ms7721/BiosCallOuts.c
M src/mainboard/msi/ms7721/OemCustomize.c
M src/mainboard/msi/ms7721/buildOpts.c
M src/mainboard/msi/ms7721/romstage.c
M src/mainboard/msi/ms9652_fam10/get_bus_conf.c
M src/mainboard/msi/ms9652_fam10/romstage.c
M src/mainboard/ocp/monolake/mainboard.c
M src/mainboard/ocp/wedge100s/mainboard.c
M src/mainboard/ocp/wedge100s/romstage.c
M src/mainboard/opencellular/elgon/bootblock.c
M src/mainboard/pcengines/apu2/BiosCallOuts.c
M src/mainboard/pcengines/apu2/mainboard.c
M src/mainboard/pcengines/apu2/romstage.c
M src/mainboard/samsung/lumpy/acpi_tables.c
M src/mainboard/samsung/lumpy/romstage.c
M src/mainboard/samsung/stumpy/romstage.c
M src/mainboard/scaleway/tagada/bootblock.c
M src/mainboard/siemens/mc_bdx1/mainboard.c
M src/mainboard/siemens/mc_tcu3/mainboard.c
M src/mainboard/sifive/hifive-unleashed/romstage.c
M src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c
M src/mainboard/supermicro/h8dmr_fam10/romstage.c
M src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c
M src/mainboard/supermicro/h8qme_fam10/romstage.c
M src/mainboard/supermicro/h8scm_fam10/romstage.c
M src/mainboard/tyan/s2912_fam10/get_bus_conf.c
M src/mainboard/tyan/s2912_fam10/romstage.c
M src/mainboard/via/epia-m850/mainboard.c
M src/northbridge/amd/agesa/family12/northbridge.c
M src/northbridge/amd/agesa/family14/northbridge.c
M src/northbridge/amd/agesa/family15tn/northbridge.c
M src/northbridge/amd/agesa/family16kb/northbridge.c
M src/northbridge/amd/agesa/family16kb/state_machine.c
M src/northbridge/amd/agesa/state_machine.h
M src/northbridge/amd/amdfam10/debug.c
M src/northbridge/amd/amdfam10/debug.h
M src/northbridge/amd/amdfam10/early_ht.c
M src/northbridge/amd/amdfam10/link_control.c
M src/northbridge/amd/amdfam10/misc_control.c
M src/northbridge/amd/amdfam10/northbridge.c
M src/northbridge/amd/amdfam10/raminit_amdmct.c
M src/northbridge/amd/amdht/h3finit.c
M src/northbridge/amd/amdht/ht_wrapper.c
M src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
M src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
M src/northbridge/amd/amdmct/wrappers/mcti.h
M src/northbridge/amd/amdmct/wrappers/mcti_d.c
M src/northbridge/amd/pi/00630F01/northbridge.c
M src/northbridge/amd/pi/00660F01/northbridge.c
M src/northbridge/amd/pi/00730F01/northbridge.c
M src/northbridge/amd/pi/agesawrapper.c
M src/northbridge/amd/pi/agesawrapper.h
M src/northbridge/intel/e7505/raminit.c
M src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c
M src/northbridge/intel/gm45/gma.c
M src/northbridge/intel/haswell/acpi/haswell.asl
M src/northbridge/intel/haswell/gma.c
M src/northbridge/intel/haswell/northbridge.c
M src/northbridge/intel/i440bx/raminit.c
M src/northbridge/intel/i440bx/raminit.h
M src/northbridge/intel/i945/early_init.c
M src/northbridge/intel/i945/gma.c
M src/northbridge/intel/i945/raminit.c
M src/northbridge/intel/i945/raminit.h
M src/northbridge/intel/nehalem/acpi/nehalem.asl
M src/northbridge/intel/nehalem/early_init.c
M src/northbridge/intel/nehalem/gma.c
M src/northbridge/intel/nehalem/northbridge.c
M src/northbridge/intel/pineview/gma.c
M src/northbridge/intel/pineview/raminit.c
M src/northbridge/intel/sandybridge/acpi/sandybridge.asl
M src/northbridge/intel/sandybridge/early_init.c
M src/northbridge/intel/sandybridge/gma.c
M src/northbridge/intel/sandybridge/northbridge.c
M src/northbridge/intel/sandybridge/pcie.c
M src/northbridge/intel/sandybridge/raminit.c
M src/northbridge/intel/sandybridge/raminit_common.c
M src/northbridge/intel/sandybridge/raminit_mrc.c
M src/northbridge/intel/x4x/early_init.c
M src/northbridge/intel/x4x/gma.c
M src/northbridge/intel/x4x/raminit.c
M src/northbridge/intel/x4x/raminit_ddr23.c
M src/northbridge/via/vx900/lpc.c
M src/security/tpm/tspi/log.c
M src/security/tpm/tspi/tspi.c
M src/security/tpm/tss.h
M src/security/vboot/bootmode.c
M src/security/vboot/common.c
M src/security/vboot/secdata_tpm.c
M src/security/vboot/vbnv.c
M src/security/vboot/vbnv_cmos.c
M src/security/vboot/vboot_common.c
M src/security/vboot/vboot_common.h
M src/security/vboot/vboot_crtm.c
M src/security/vboot/vboot_crtm.h
M src/security/vboot/vboot_handoff.c
M src/security/vboot/vboot_loader.c
M src/security/vboot/vboot_logic.c
M src/security/vboot/verstage.c
M src/soc/amd/common/block/pi/refcode_loader.c
M src/soc/amd/common/block/psp/psp.c
M src/soc/amd/stoneyridge/BiosCallOuts.c
M src/soc/amd/stoneyridge/acpi.c
M src/soc/amd/stoneyridge/acpi/sleepstates.asl
M src/soc/amd/stoneyridge/bootblock/bootblock.c
M src/soc/amd/stoneyridge/chip.c
M src/soc/amd/stoneyridge/finalize.c
M src/soc/amd/stoneyridge/include/soc/acpi.h
M src/soc/amd/stoneyridge/include/soc/iomap.h
M src/soc/amd/stoneyridge/lpc.c
M src/soc/amd/stoneyridge/mca.c
M src/soc/amd/stoneyridge/northbridge.c
M src/soc/amd/stoneyridge/ramtop.c
M src/soc/amd/stoneyridge/romstage.c
M src/soc/amd/stoneyridge/smihandler.c
M src/soc/amd/stoneyridge/southbridge.c
M src/soc/amd/stoneyridge/spi.c
M src/soc/cavium/cn81xx/soc.c
M src/soc/cavium/common/bootblock.c
M src/soc/intel/apollolake/acpi.c
M src/soc/intel/apollolake/acpi/pci_irqs.asl
M src/soc/intel/apollolake/acpi/southbridge.asl
M src/soc/intel/apollolake/acpi/xhci.asl
M src/soc/intel/apollolake/bootblock/bootblock.c
M src/soc/intel/apollolake/chip.c
M src/soc/intel/apollolake/cpu.c
M src/soc/intel/apollolake/cse.c
M src/soc/intel/apollolake/graphics.c
M src/soc/intel/apollolake/include/soc/gpio.h
M src/soc/intel/apollolake/include/soc/pcr_ids.h
M src/soc/intel/apollolake/include/soc/pm.h
M src/soc/intel/apollolake/lpc.c
M src/soc/intel/apollolake/meminit.c
M src/soc/intel/apollolake/memmap.c
M src/soc/intel/apollolake/romstage.c
M src/soc/intel/apollolake/smihandler.c
M src/soc/intel/apollolake/uart.c
M src/soc/intel/baytrail/acpi.c
M src/soc/intel/baytrail/include/soc/pmc.h
M src/soc/intel/baytrail/include/soc/ramstage.h
M src/soc/intel/baytrail/include/soc/romstage.h
M src/soc/intel/baytrail/northcluster.c
M src/soc/intel/baytrail/romstage/raminit.c
M src/soc/intel/baytrail/romstage/romstage.c
M src/soc/intel/baytrail/smihandler.c
M src/soc/intel/baytrail/spi.c
M src/soc/intel/braswell/acpi.c
M src/soc/intel/braswell/acpi/lpc.asl
M src/soc/intel/braswell/gfx.c
M src/soc/intel/braswell/include/soc/pm.h
M src/soc/intel/braswell/memmap.c
M src/soc/intel/braswell/northcluster.c
M src/soc/intel/braswell/romstage/romstage.c
M src/soc/intel/braswell/smihandler.c
M src/soc/intel/braswell/spi.c
M src/soc/intel/broadwell/acpi.c
M src/soc/intel/broadwell/chip.c
M src/soc/intel/broadwell/finalize.c
M src/soc/intel/broadwell/igd.c
M src/soc/intel/broadwell/include/soc/ramstage.h
M src/soc/intel/broadwell/lpc.c
M src/soc/intel/broadwell/me.c
M src/soc/intel/broadwell/pcie.c
M src/soc/intel/broadwell/romstage/power_state.c
M src/soc/intel/broadwell/romstage/raminit.c
M src/soc/intel/broadwell/romstage/romstage.c
M src/soc/intel/broadwell/serialio.c
M src/soc/intel/broadwell/smihandler.c
M src/soc/intel/broadwell/spi.c
M src/soc/intel/broadwell/systemagent.c
M src/soc/intel/cannonlake/acpi.c
M src/soc/intel/cannonlake/acpi/scs.asl
M src/soc/intel/cannonlake/acpi/southbridge.asl
M src/soc/intel/cannonlake/bootblock/bootblock.c
M src/soc/intel/cannonlake/bootblock/cpu.c
M src/soc/intel/cannonlake/bootblock/pch.c
M src/soc/intel/cannonlake/chip.c
M src/soc/intel/cannonlake/chip.h
M src/soc/intel/cannonlake/cnl_memcfg_init.c
M src/soc/intel/cannonlake/cpu.c
M src/soc/intel/cannonlake/fsp_params.c
M src/soc/intel/cannonlake/graphics.c
M src/soc/intel/cannonlake/include/soc/gpio.h
M src/soc/intel/cannonlake/include/soc/pmc.h
M src/soc/intel/cannonlake/include/soc/smm.h
M src/soc/intel/cannonlake/lpc.c
M src/soc/intel/cannonlake/memmap.c
M src/soc/intel/cannonlake/romstage/fsp_params.c
M src/soc/intel/cannonlake/smihandler.c
M src/soc/intel/common/acpi/acpi_debug.asl
M src/soc/intel/common/acpi/platform.asl
M src/soc/intel/common/block/acpi/acpi.c
M src/soc/intel/common/block/cpu/car/cache_as_ram.S
M src/soc/intel/common/block/cpu/car/exit_car.S
M src/soc/intel/common/block/fast_spi/fast_spi.c
M src/soc/intel/common/block/gpio/gpio.c
M src/soc/intel/common/block/gspi/gspi.c
M src/soc/intel/common/block/hda/hda.c
M src/soc/intel/common/block/include/intelblocks/gpio_defs.h
M src/soc/intel/common/block/lpc/lpc_lib.c
M src/soc/intel/common/block/pcie/pcie.c
M src/soc/intel/common/block/pcr/pcr.c
M src/soc/intel/common/block/pmc/pmc.c
M src/soc/intel/common/block/pmc/pmclib.c
M src/soc/intel/common/block/rtc/rtc.c
M src/soc/intel/common/block/sata/sata.c
M src/soc/intel/common/block/scs/sd.c
M src/soc/intel/common/block/smbus/tco.c
M src/soc/intel/common/block/smm/smihandler.c
M src/soc/intel/common/block/smm/smm.c
M src/soc/intel/common/block/spi/spi.c
M src/soc/intel/common/block/systemagent/systemagent.c
M src/soc/intel/common/block/uart/uart.c
M src/soc/intel/common/block/xhci/xhci.c
M src/soc/intel/common/pch/lockdown/lockdown.c
M src/soc/intel/common/vbt.c
M src/soc/intel/denverton_ns/acpi.c
M src/soc/intel/denverton_ns/bootblock/bootblock.c
M src/soc/intel/denverton_ns/bootblock/uart.c
M src/soc/intel/denverton_ns/chip.c
M src/soc/intel/denverton_ns/hob_mem.c
M src/soc/intel/denverton_ns/include/soc/pmc.h
M src/soc/intel/denverton_ns/lpc.c
M src/soc/intel/denverton_ns/memmap.c
M src/soc/intel/denverton_ns/pmc.c
M src/soc/intel/denverton_ns/romstage.c
M src/soc/intel/denverton_ns/smihandler.c
M src/soc/intel/denverton_ns/uart.c
M src/soc/intel/fsp_baytrail/acpi.c
M src/soc/intel/fsp_baytrail/acpi/sleepstates.asl
M src/soc/intel/fsp_baytrail/cpu.c
M src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c
M src/soc/intel/fsp_baytrail/gpio.c
M src/soc/intel/fsp_baytrail/include/soc/pmc.h
M src/soc/intel/fsp_baytrail/include/soc/romstage.h
M src/soc/intel/fsp_baytrail/romstage/romstage.c
M src/soc/intel/fsp_baytrail/smihandler.c
M src/soc/intel/fsp_baytrail/southcluster.c
M src/soc/intel/fsp_baytrail/spi.c
M src/soc/intel/fsp_broadwell_de/chip.c
M src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c
M src/soc/intel/fsp_broadwell_de/romstage/romstage.c
M src/soc/intel/fsp_broadwell_de/southcluster.c
M src/soc/intel/icelake/acpi.c
M src/soc/intel/icelake/bootblock/bootblock.c
M src/soc/intel/icelake/bootblock/cpu.c
M src/soc/intel/icelake/bootblock/pch.c
M src/soc/intel/icelake/chip.c
M src/soc/intel/icelake/graphics.c
M src/soc/intel/icelake/include/soc/smm.h
M src/soc/intel/icelake/lpc.c
M src/soc/intel/icelake/memmap.c
M src/soc/intel/icelake/smihandler.c
M src/soc/intel/quark/bootblock/bootblock.c
M src/soc/intel/quark/bootblock/esram_init.S
M src/soc/intel/quark/i2c.c
M src/soc/intel/quark/romstage/car.c
M src/soc/intel/quark/romstage/car_stage_entry.S
M src/soc/intel/quark/romstage/fsp2_0.c
M src/soc/intel/quark/sd.c
M src/soc/intel/quark/storage_test.c
M src/soc/intel/skylake/acpi.c
M src/soc/intel/skylake/acpi/gpio.asl
M src/soc/intel/skylake/acpi/pch.asl
M src/soc/intel/skylake/acpi/scs.asl
M src/soc/intel/skylake/bootblock/bootblock.c
M src/soc/intel/skylake/bootblock/pch.c
M src/soc/intel/skylake/chip.c
M src/soc/intel/skylake/chip_fsp20.c
M src/soc/intel/skylake/cpu.c
M src/soc/intel/skylake/gpio.c
M src/soc/intel/skylake/graphics.c
M src/soc/intel/skylake/include/soc/bootblock.h
M src/soc/intel/skylake/include/soc/gpio_defs.h
M src/soc/intel/skylake/include/soc/pm.h
M src/soc/intel/skylake/include/soc/smm.h
M src/soc/intel/skylake/include/soc/vr_config.h
M src/soc/intel/skylake/me.c
M src/soc/intel/skylake/memmap.c
M src/soc/intel/skylake/romstage/car_stage.S
M src/soc/intel/skylake/romstage/romstage.c
M src/soc/intel/skylake/romstage/romstage_fsp20.c
M src/soc/intel/skylake/smihandler.c
M src/soc/intel/skylake/vr_config.c
M src/soc/mediatek/mt8173/i2c.c
M src/soc/mediatek/mt8173/include/soc/dramc_pi_api.h
M src/soc/mediatek/mt8173/memory.c
M src/soc/mediatek/mt8173/mt6391.c
M src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h
M src/soc/mediatek/mt8183/memory.c
M src/soc/nvidia/tegra210/ccplex.c
M src/soc/nvidia/tegra210/include/soc/console_uart.h
M src/soc/nvidia/tegra210/include/soc/mtc.h
M src/soc/nvidia/tegra210/romstage.c
M src/soc/nvidia/tegra210/soc.c
M src/soc/qualcomm/ipq40xx/uart.c
M src/soc/rockchip/common/gpio.c
M src/soc/rockchip/common/pwm.c
M src/soc/rockchip/rk3399/clock.c
M src/soc/rockchip/rk3399/soc.c
M src/southbridge/amd/agesa/hudson/acpi/fch.asl
M src/southbridge/amd/agesa/hudson/acpi/usb.asl
M src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h
M src/southbridge/amd/agesa/hudson/amd_pci_int_types.h
M src/southbridge/amd/agesa/hudson/fadt.c
M src/southbridge/amd/agesa/hudson/hudson.c
M src/southbridge/amd/agesa/hudson/imc.c
M src/southbridge/amd/agesa/hudson/lpc.c
M src/southbridge/amd/agesa/hudson/pci_devs.h
M src/southbridge/amd/agesa/hudson/resume.c
M src/southbridge/amd/agesa/hudson/sata.c
M src/southbridge/amd/agesa/hudson/spi.c
M src/southbridge/amd/amd8111/acpi.c
M src/southbridge/amd/amd8111/acpi/sleepstates.asl
M src/southbridge/amd/amd8111/lpc.c
M src/southbridge/amd/cimx/sb800/SBPLATFORM.h
M src/southbridge/amd/cimx/sb800/bootblock.c
M src/southbridge/amd/cimx/sb800/late.c
M src/southbridge/amd/cimx/sb800/spi.c
M src/southbridge/amd/cimx/sb900/late.c
M src/southbridge/amd/common/acpi/sleepstates.asl
M src/southbridge/amd/pi/hudson/acpi/fch.asl
M src/southbridge/amd/pi/hudson/acpi/usb.asl
M src/southbridge/amd/pi/hudson/amd_pci_int_defs.h
M src/southbridge/amd/pi/hudson/amd_pci_int_types.h
M src/southbridge/amd/pi/hudson/early_setup.c
M src/southbridge/amd/pi/hudson/fadt.c
M src/southbridge/amd/pi/hudson/gpio.h
M src/southbridge/amd/pi/hudson/hudson.c
M src/southbridge/amd/pi/hudson/hudson.h
M src/southbridge/amd/pi/hudson/lpc.c
M src/southbridge/amd/pi/hudson/pci_devs.h
M src/southbridge/amd/pi/hudson/sata.c
M src/southbridge/amd/rs780/cmn.c
M src/southbridge/amd/rs780/early_setup.c
M src/southbridge/amd/rs780/gfx.c
M src/southbridge/amd/rs780/rs780.c
M src/southbridge/amd/sb700/bootblock.c
M src/southbridge/amd/sb700/early_setup.c
M src/southbridge/amd/sb700/fadt.c
M src/southbridge/amd/sb700/lpc.c
M src/southbridge/amd/sb700/sata.c
M src/southbridge/amd/sb700/sb700.c
M src/southbridge/amd/sb700/sm.c
M src/southbridge/amd/sb700/usb.c
M src/southbridge/amd/sb800/fadt.c
M src/southbridge/amd/sb800/lpc.c
M src/southbridge/amd/sr5650/early_setup.c
M src/southbridge/amd/sr5650/ht.c
M src/southbridge/amd/sr5650/sr5650.c
M src/southbridge/intel/bd82x6x/lpc.c
M src/southbridge/intel/bd82x6x/me.c
M src/southbridge/intel/bd82x6x/me_8.x.c
M src/southbridge/intel/bd82x6x/pch.h
M src/southbridge/intel/bd82x6x/usb_ehci.c
M src/southbridge/intel/common/finalize.c
M src/southbridge/intel/common/pmutil.h
M src/southbridge/intel/common/rtc.c
M src/southbridge/intel/common/smbus.c
M src/southbridge/intel/common/smi.c
M src/southbridge/intel/common/smihandler.c
M src/southbridge/intel/common/spi.c
M src/southbridge/intel/common/usb_debug.c
M src/southbridge/intel/fsp_rangeley/acpi.c
M src/southbridge/intel/fsp_rangeley/lpc.c
M src/southbridge/intel/fsp_rangeley/romstage.c
M src/southbridge/intel/fsp_rangeley/soc.h
M src/southbridge/intel/fsp_rangeley/spi.c
M src/southbridge/intel/i82371eb/isa.c
M src/southbridge/intel/i82801gx/lpc.c
M src/southbridge/intel/i82801ix/acpi/sleepstates.asl
M src/southbridge/intel/i82801ix/i82801ix.c
M src/southbridge/intel/i82801ix/i82801ix.h
M src/southbridge/intel/i82801ix/lpc.c
M src/southbridge/intel/i82801jx/acpi/sleepstates.asl
M src/southbridge/intel/i82801jx/i82801jx.c
M src/southbridge/intel/i82801jx/lpc.c
M src/southbridge/intel/ibexpeak/lpc.c
M src/southbridge/intel/ibexpeak/me.c
M src/southbridge/intel/ibexpeak/pch.h
M src/southbridge/intel/ibexpeak/smi.c
M src/southbridge/intel/ibexpeak/smihandler.c
M src/southbridge/intel/lynxpoint/acpi/pch.asl
M src/southbridge/intel/lynxpoint/early_pch.c
M src/southbridge/intel/lynxpoint/lpc.c
M src/southbridge/intel/lynxpoint/me_9.x.c
M src/southbridge/intel/lynxpoint/pch.h
M src/southbridge/intel/lynxpoint/pmutil.c
M src/southbridge/intel/lynxpoint/smi.c
M src/southbridge/intel/lynxpoint/smihandler.c
M src/southbridge/nvidia/ck804/early_setup_car.c
M src/southbridge/nvidia/ck804/ht.c
M src/southbridge/nvidia/ck804/lpc.c
M src/southbridge/nvidia/mcp55/azalia.c
M src/southbridge/nvidia/mcp55/early_setup_car.c
M src/southbridge/nvidia/mcp55/ht.c
M src/southbridge/nvidia/mcp55/lpc.c
M src/southbridge/nvidia/mcp55/smbus.c
M src/superio/ite/common/env_ctrl.c
M src/superio/ite/common/env_ctrl.h
M src/superio/ite/common/env_ctrl_chip.h
M src/superio/ite/it8716f/superio.c
M src/superio/nuvoton/common/early_serial.c
M src/superio/nuvoton/npcd378/superio.c
M src/superio/via/vt1211/superio.c
M src/vendorcode/amd/agesa/common/agesa-entry-cfg.h
M src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mp.c
M src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc
M src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc
M src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc
M src/vendorcode/cavium/bdk/libdram/libdram.c
M src/vendorcode/cavium/include/bdk/libbdk-arch/bdk-warn.h
M src/vendorcode/google/chromeos/acpi.c
M src/vendorcode/google/chromeos/acpi/chromeos.asl
M src/vendorcode/google/chromeos/chromeos.h
M src/vendorcode/google/chromeos/cr50_enable_update.c
M src/vendorcode/google/chromeos/elog.c
M src/vendorcode/google/chromeos/ramoops.c
M src/vendorcode/google/chromeos/sar.c
M src/vendorcode/google/chromeos/tpm2.c
920 files changed, 2,285 insertions(+), 2,285 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/31774/3

[build bot (Jenkins) (Code Review)]

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31774 )

Change subject: coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)
......................................................................

Patch Set 3:

(28 comments)

https://review.coreboot.org/#/c/31774/3/src/console/printk.c 
File src/console/printk.c:

https://review.coreboot.org/#/c/31774/3/src/console/printk.c@29 
PS3, Line 29: #if (!defined(__PRE_RAM__) && CONFIG(HAVE_ROMSTAGE_CONSOLE_SPINLOCK)) || !CONFIG(HAVE_ROMSTAGE_CONSOLE_SPINLOCK)
line over 96 characters

https://review.coreboot.org/#/c/31774/3/src/cpu/amd/pi/00630F01/fixme.c 
File src/cpu/amd/pi/00630F01/fixme.c:

https://review.coreboot.org/#/c/31774/3/src/cpu/amd/pi/00630F01/fixme.c@91 
PS3, Line 91: 	if (CONFIG(UDELAY_LAPIC)){
space required before the open brace '{'

https://review.coreboot.org/#/c/31774/3/src/device/pci_rom.c 
File src/device/pci_rom.c:

https://review.coreboot.org/#/c/31774/3/src/device/pci_rom.c@58 
PS3, Line 58: 	} else if (!CONFIG(ON_DEVICE_ROM_LOAD)) {
suspect code indent for conditional statements (8, 24)

https://review.coreboot.org/#/c/31774/3/src/drivers/pc80/tpm/tis.c 
File src/drivers/pc80/tpm/tis.c:

https://review.coreboot.org/#/c/31774/3/src/drivers/pc80/tpm/tis.c@129 
PS3, Line 129: #if CONFIG(TPM2)
braces {} are not necessary for single statement blocks

https://review.coreboot.org/#/c/31774/3/src/drivers/spi/spi_flash.c 
File src/drivers/spi/spi_flash.c:

https://review.coreboot.org/#/c/31774/3/src/drivers/spi/spi_flash.c@279 
PS3, Line 279: #if CONFIG(SPI_FLASH_AMIC)
braces {} are not necessary for single statement blocks

https://review.coreboot.org/#/c/31774/3/src/drivers/spi/spi_flash.c@282 
PS3, Line 282: #if CONFIG(SPI_FLASH_ATMEL)
braces {} are not necessary for single statement blocks

https://review.coreboot.org/#/c/31774/3/src/drivers/spi/spi_flash.c@285 
PS3, Line 285: #if CONFIG(SPI_FLASH_EON)
braces {} are not necessary for single statement blocks

https://review.coreboot.org/#/c/31774/3/src/drivers/spi/spi_flash.c@288 
PS3, Line 288: #if CONFIG(SPI_FLASH_GIGADEVICE)
braces {} are not necessary for single statement blocks

https://review.coreboot.org/#/c/31774/3/src/drivers/spi/spi_flash.c@291 
PS3, Line 291: #if CONFIG(SPI_FLASH_MACRONIX)
braces {} are not necessary for single statement blocks

https://review.coreboot.org/#/c/31774/3/src/drivers/spi/spi_flash.c@294 
PS3, Line 294: #if CONFIG(SPI_FLASH_SPANSION)
braces {} are not necessary for single statement blocks

https://review.coreboot.org/#/c/31774/3/src/drivers/spi/spi_flash.c@297 
PS3, Line 297: #if CONFIG(SPI_FLASH_SST)
braces {} are not necessary for single statement blocks

https://review.coreboot.org/#/c/31774/3/src/drivers/spi/spi_flash.c@300 
PS3, Line 300: #if CONFIG(SPI_FLASH_STMICRO)
braces {} are not necessary for single statement blocks

https://review.coreboot.org/#/c/31774/3/src/drivers/spi/spi_flash.c@303 
PS3, Line 303: #if CONFIG(SPI_FLASH_WINBOND)
braces {} are not necessary for single statement blocks

https://review.coreboot.org/#/c/31774/3/src/drivers/spi/spi_flash.c@307 
PS3, Line 307: #if CONFIG(SPI_FLASH_STMICRO)
braces {} are not necessary for single statement blocks

https://review.coreboot.org/#/c/31774/3/src/drivers/spi/spi_flash.c@310 
PS3, Line 310: #if CONFIG(SPI_FLASH_ADESTO)
braces {} are not necessary for single statement blocks

https://review.coreboot.org/#/c/31774/3/src/lib/prog_loaders.c 
File src/lib/prog_loaders.c:

https://review.coreboot.org/#/c/31774/3/src/lib/prog_loaders.c@84 
PS3, Line 84: 	if (CONFIG(RESET_ON_INVALID_RAMSTAGE_CACHE)) {
braces {} are not necessary for single statement blocks

https://review.coreboot.org/#/c/31774/3/src/mainboard/amd/lamar/OemCustomize... 
File src/mainboard/amd/lamar/OemCustomize.c:

https://review.coreboot.org/#/c/31774/3/src/mainboard/amd/lamar/OemCustomize... 
PS3, Line 61: 				CONFIG(ENABLE_DP3_DAUGHTER_CARD_IN_J120) ? PcieUnusedEngine : PciePortEngine,
line over 96 characters

https://review.coreboot.org/#/c/31774/3/src/mainboard/amd/lamar/OemCustomize... 
PS3, Line 81: 				CONFIG(ENABLE_DP3_DAUGHTER_CARD_IN_J120) ? PcieDdiEngine : PcieUnusedEngine,
line over 96 characters

https://review.coreboot.org/#/c/31774/3/src/mainboard/emulation/qemu-power8/... 
File src/mainboard/emulation/qemu-power8/bootblock.c:

https://review.coreboot.org/#/c/31774/3/src/mainboard/emulation/qemu-power8/... 
PS3, Line 25: 	if (CONFIG(BOOTBLOCK_CONSOLE)) {
braces {} are not necessary for single statement blocks

https://review.coreboot.org/#/c/31774/3/src/mainboard/google/gru/chromeos.c 
File src/mainboard/google/gru/chromeos.c:

https://review.coreboot.org/#/c/31774/3/src/mainboard/google/gru/chromeos.c@... 
PS3, Line 39: #if CONFIG(GRU_BASEBOARD_SCARLET)
braces {} are not necessary for single statement blocks

https://review.coreboot.org/#/c/31774/3/src/mainboard/google/gru/chromeos.c@... 
PS3, Line 46: #if CONFIG(GRU_HAS_TPM2)
braces {} are not necessary for single statement blocks

https://review.coreboot.org/#/c/31774/3/src/mainboard/google/jecht/smihandle... 
File src/mainboard/google/jecht/smihandler.c:

https://review.coreboot.org/#/c/31774/3/src/mainboard/google/jecht/smihandle... 
PS3, Line 62: 		if (CONFIG(BOARD_GOOGLE_TIDUS)) {
braces {} are not necessary for single statement blocks

https://review.coreboot.org/#/c/31774/3/src/mainboard/pcengines/apu2/romstag... 
File src/mainboard/pcengines/apu2/romstage.c:

https://review.coreboot.org/#/c/31774/3/src/mainboard/pcengines/apu2/romstag... 
PS3, Line 146: 	if (CONFIG(BOARD_PCENGINES_APU5)) {
braces {} are not necessary for single statement blocks

https://review.coreboot.org/#/c/31774/3/src/northbridge/intel/haswell/gma.c 
File src/northbridge/intel/haswell/gma.c:

https://review.coreboot.org/#/c/31774/3/src/northbridge/intel/haswell/gma.c@... 
PS3, Line 243: 	if (CONFIG(MAINBOARD_DO_NATIVE_VGA_INIT)) {
braces {} are not necessary for single statement blocks

https://review.coreboot.org/#/c/31774/3/src/soc/intel/cannonlake/acpi.c 
File src/soc/intel/cannonlake/acpi.c:

https://review.coreboot.org/#/c/31774/3/src/soc/intel/cannonlake/acpi.c@207 
PS3, Line 207: 	if (CONFIG(CONSOLE_CBMEM))
suspect code indent for conditional statements (8, 8)

https://review.coreboot.org/#/c/31774/3/src/soc/intel/quark/storage_test.c 
File src/soc/intel/quark/storage_test.c:

https://review.coreboot.org/#/c/31774/3/src/soc/intel/quark/storage_test.c@1... 
PS3, Line 136: 	if (CONFIG(STORAGE_LOG)) {
braces {} are not necessary for single statement blocks

https://review.coreboot.org/#/c/31774/3/src/soc/intel/skylake/gpio.c 
File src/soc/intel/skylake/gpio.c:

https://review.coreboot.org/#/c/31774/3/src/soc/intel/skylake/gpio.c@162 
PS3, Line 162: #if CONFIG(SKYLAKE_SOC_PCH_H)
braces {} are not necessary for single statement blocks

https://review.coreboot.org/#/c/31774/3/src/southbridge/amd/sb700/sm.c 
File src/southbridge/amd/sb700/sm.c:

https://review.coreboot.org/#/c/31774/3/src/southbridge/amd/sb700/sm.c@308 
PS3, Line 308: 	if (CONFIG(ENABLE_APIC_EXT_ID))
suspect code indent for conditional statements (8, 8)

[Julius Werner (Code Review)]

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31774 )

Change subject: coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)
......................................................................

Patch Set 3:

Updated. (Don't worry about nefarious changes, whenever I do those I rather just git force push them and put your author tag on it. :P )

[Patrick Georgi (Code Review)]

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31774 )

Change subject: coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)
......................................................................

Patch Set 3: Code-Review+2

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31774 )

Change subject: coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)
......................................................................

coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)

This patch is a raw application of

find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'

Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) 
Reviewed-by: Patrick Georgi 
---
M src/arch/arm/armv7/mmu.c
M src/arch/arm/include/arch/memlayout.h
M src/arch/arm/include/armv7/arch/cache.h
M src/arch/arm/tables.c
M src/arch/arm64/arm_tf.c
M src/arch/arm64/armv8/exception.c
M src/arch/arm64/boot.c
M src/arch/arm64/include/armv8/arch/barrier.h
M src/arch/arm64/tables.c
M src/arch/mips/bootblock_simple.c
M src/arch/ppc64/include/arch/cpu.h
M src/arch/riscv/include/arch/cpu.h
M src/arch/riscv/sbi.c
M src/arch/x86/acpi.c
M src/arch/x86/acpi_device.c
M src/arch/x86/acpi_s3.c
M src/arch/x86/assembly_entry.S
M src/arch/x86/bootblock.ld
M src/arch/x86/bootblock_crt0.S
M src/arch/x86/bootblock_romcc.S
M src/arch/x86/bootblock_simple.c
M src/arch/x86/c_start.S
M src/arch/x86/car.ld
M src/arch/x86/cbmem.c
M src/arch/x86/cpu.c
M src/arch/x86/exception.c
M src/arch/x86/exit_car.S
M src/arch/x86/gdt.c
M src/arch/x86/include/arch/acpi.h
M src/arch/x86/include/arch/cpu.h
M src/arch/x86/include/arch/early_variables.h
M src/arch/x86/include/arch/exception.h
M src/arch/x86/include/arch/interrupt.h
M src/arch/x86/include/arch/pci_io_cfg.h
M src/arch/x86/include/arch/registers.h
M src/arch/x86/include/arch/smp/spinlock.h
M src/arch/x86/include/cf9_reset.h
M src/arch/x86/ioapic.c
M src/arch/x86/memlayout.ld
M src/arch/x86/pci_ops_conf1.c
M src/arch/x86/pirq_routing.c
M src/arch/x86/postcar_loader.c
M src/arch/x86/smbios.c
M src/arch/x86/tables.c
M src/arch/x86/timestamp.c
M src/commonlib/cbfs.c
M src/commonlib/include/commonlib/stdlib.h
M src/commonlib/storage/mmc.c
M src/commonlib/storage/sd_mmc.c
M src/commonlib/storage/sd_mmc.h
M src/commonlib/storage/sdhci.c
M src/commonlib/storage/sdhci_display.c
M src/commonlib/storage/storage.c
M src/console/console.c
M src/console/init.c
M src/console/post.c
M src/console/printk.c
M src/console/vtxprintf.c
M src/cpu/amd/agesa/family12/model_12_init.c
M src/cpu/amd/agesa/family14/model_14_init.c
M src/cpu/amd/agesa/family15tn/model_15_init.c
M src/cpu/amd/agesa/family16kb/model_16_init.c
M src/cpu/amd/car/cache_as_ram.inc
M src/cpu/amd/car/disable_cache_as_ram.c
M src/cpu/amd/car/post_cache_as_ram.c
M src/cpu/amd/family_10h-family_15h/fidvid.c
M src/cpu/amd/family_10h-family_15h/init_cpus.c
M src/cpu/amd/family_10h-family_15h/model_10xxx_init.c
M src/cpu/amd/family_10h-family_15h/powernow_acpi.c
M src/cpu/amd/family_10h-family_15h/ram_calc.c
M src/cpu/amd/microcode/microcode.c
M src/cpu/amd/pi/00630F01/fixme.c
M src/cpu/amd/pi/00630F01/model_15_init.c
M src/cpu/amd/pi/00660F01/fixme.c
M src/cpu/amd/pi/00660F01/model_15_init.c
M src/cpu/amd/pi/00730F01/fixme.c
M src/cpu/amd/pi/00730F01/model_16_init.c
M src/cpu/amd/quadcore/quadcore.c
M src/cpu/intel/car/non-evict/cache_as_ram.S
M src/cpu/intel/car/p4-netburst/cache_as_ram.S
M src/cpu/intel/car/romstage.c
M src/cpu/intel/common/common_init.c
M src/cpu/intel/fsp_model_406dx/model_406dx_init.c
M src/cpu/intel/haswell/bootblock.c
M src/cpu/intel/haswell/romstage.c
M src/cpu/intel/hyperthreading/intel_sibling.c
M src/cpu/intel/model_1067x/mp_init.c
M src/cpu/intel/model_2065x/bootblock.c
M src/cpu/intel/model_206ax/bootblock.c
M src/cpu/intel/model_f3x/model_f3x_init.c
M src/cpu/intel/smm/gen1/smmrelocate.c
M src/cpu/intel/turbo/turbo.c
M src/cpu/x86/16bit/entry16.inc
M src/cpu/x86/32bit/entry32.inc
M src/cpu/x86/backup_default_smm.c
M src/cpu/x86/car.c
M src/cpu/x86/lapic/apic_timer.c
M src/cpu/x86/lapic/boot_cpu.c
M src/cpu/x86/lapic/lapic_cpu_init.c
M src/cpu/x86/mp_init.c
M src/cpu/x86/mtrr/debug.c
M src/cpu/x86/mtrr/mtrr.c
M src/cpu/x86/sipi_vector.S
M src/cpu/x86/smm/smihandler.c
M src/cpu/x86/smm/smm_module_handler.c
M src/cpu/x86/smm/smm_module_loader.c
M src/cpu/x86/smm/smmhandler.S
M src/cpu/x86/smm/smmrelocate.S
M src/cpu/x86/tsc/delay_tsc.c
M src/device/device.c
M src/device/device_const.c
M src/device/oprom/include/io.h
M src/device/oprom/include/x86emu/fpu_regs.h
M src/device/oprom/include/x86emu/regs.h
M src/device/oprom/include/x86emu/x86emu.h
M src/device/oprom/realmode/x86.c
M src/device/oprom/realmode/x86_interrupts.c
M src/device/oprom/yabel/biosemu.c
M src/device/oprom/yabel/compat/functions.c
M src/device/oprom/yabel/debug.h
M src/device/oprom/yabel/device.c
M src/device/oprom/yabel/device.h
M src/device/oprom/yabel/interrupt.c
M src/device/oprom/yabel/io.c
M src/device/oprom/yabel/mem.c
M src/device/oprom/yabel/vbe.c
M src/device/pci_device.c
M src/device/pci_rom.c
M src/device/pciexp_device.c
M src/device/root_device.c
M src/drivers/amd/agesa/acpi_tables.c
M src/drivers/amd/agesa/cache_as_ram.S
M src/drivers/amd/agesa/def_callouts.c
M src/drivers/amd/agesa/eventlog.c
M src/drivers/amd/agesa/heapmanager.c
M src/drivers/amd/agesa/oem_s3.c
M src/drivers/amd/agesa/romstage.c
M src/drivers/amd/agesa/state_machine.c
M src/drivers/elog/boot_count.c
M src/drivers/elog/elog.c
M src/drivers/emulation/qemu/bochs.c
M src/drivers/emulation/qemu/cirrus.c
M src/drivers/generic/adau7002/adau7002.c
M src/drivers/generic/generic/chip.h
M src/drivers/generic/max98357a/max98357a.c
M src/drivers/i2c/da7219/da7219.c
M src/drivers/i2c/designware/dw_i2c.c
M src/drivers/i2c/designware/dw_i2c.h
M src/drivers/i2c/generic/generic.c
M src/drivers/i2c/hid/hid.c
M src/drivers/i2c/nau8825/nau8825.c
M src/drivers/i2c/tpm/tis.c
M src/drivers/i2c/tpm/tis_atmel.c
M src/drivers/i2c/w83795/w83795.c
M src/drivers/intel/fsp1_0/cache_as_ram.inc
M src/drivers/intel/fsp1_0/fastboot_cache.c
M src/drivers/intel/fsp1_0/fsp_util.c
M src/drivers/intel/fsp1_0/fsp_util.h
M src/drivers/intel/fsp1_1/after_raminit.S
M src/drivers/intel/fsp1_1/cache_as_ram.inc
M src/drivers/intel/fsp1_1/fsp_util.c
M src/drivers/intel/fsp1_1/raminit.c
M src/drivers/intel/fsp1_1/ramstage.c
M src/drivers/intel/fsp1_1/romstage.c
M src/drivers/intel/fsp1_1/stack.c
M src/drivers/intel/fsp1_1/vbt.c
M src/drivers/intel/fsp2_0/debug.c
M src/drivers/intel/fsp2_0/hand_off_block.c
M src/drivers/intel/fsp2_0/include/fsp/soc_binding.h
M src/drivers/intel/fsp2_0/memory_init.c
M src/drivers/intel/fsp2_0/silicon_init.c
M src/drivers/intel/fsp2_0/util.c
M src/drivers/intel/gma/int15.h
M src/drivers/intel/gma/opregion.c
M src/drivers/intel/gma/vbt.c
M src/drivers/intel/wifi/wifi.c
M src/drivers/lenovo/wacom.c
M src/drivers/mrc_cache/mrc_cache.c
M src/drivers/net/r8168.c
M src/drivers/pc80/pc/i8254.c
M src/drivers/pc80/rtc/mc146818rtc.c
M src/drivers/pc80/rtc/mc146818rtc_boot.c
M src/drivers/pc80/rtc/mc146818rtc_romcc.c
M src/drivers/pc80/tpm/tis.c
M src/drivers/siemens/nc_fpga/nc_fpga.c
M src/drivers/smmstore/store.c
M src/drivers/spi/adesto.c
M src/drivers/spi/amic.c
M src/drivers/spi/atmel.c
M src/drivers/spi/eon.c
M src/drivers/spi/gigadevice.c
M src/drivers/spi/macronix.c
M src/drivers/spi/spansion.c
M src/drivers/spi/spi_flash.c
M src/drivers/spi/sst.c
M src/drivers/spi/stmicro.c
M src/drivers/spi/winbond.c
M src/drivers/tpm/tpm.c
M src/drivers/uart/uart8250io.c
M src/drivers/uart/uart8250mem.c
M src/drivers/uart/util.c
M src/drivers/usb/ehci_debug.c
M src/drivers/usb/gadget.c
M src/drivers/xgi/common/vb_init.c
M src/drivers/xgi/common/xgi_coreboot.c
M src/drivers/xgi/z9s/z9s.c
M src/ec/google/chromeec/acpi/ec.asl
M src/ec/google/chromeec/ec.c
M src/ec/google/chromeec/ec_i2c.c
M src/ec/google/chromeec/ec_lpc.c
M src/ec/google/chromeec/smihandler.c
M src/ec/google/chromeec/switches.c
M src/ec/google/wilco/acpi/superio.asl
M src/ec/google/wilco/bootblock.c
M src/ec/kontron/kempld/early_kempld.c
M src/ec/lenovo/h8/acpi/thinkpad.asl
M src/ec/lenovo/h8/h8.c
M src/ec/lenovo/h8/panic.c
M src/ec/quanta/ene_kb3940q/ec.c
M src/include/adainit.h
M src/include/assert.h
M src/include/bootstate.h
M src/include/cbmem.h
M src/include/console/cbmem_console.h
M src/include/console/console.h
M src/include/console/flash.h
M src/include/console/ne2k.h
M src/include/console/qemu_debugcon.h
M src/include/console/spi.h
M src/include/console/spkmodem.h
M src/include/console/uart.h
M src/include/console/usb.h
M src/include/cper.h
M src/include/cpu/x86/lapic.h
M src/include/cpu/x86/msr.h
M src/include/cpu/x86/post_code.h
M src/include/cpu/x86/smm.h
M src/include/cpu/x86/tsc.h
M src/include/device/device.h
M src/include/device/dram/common.h
M src/include/device/dram/ddr3.h
M src/include/device/early_smbus.h
M src/include/device/pci.h
M src/include/device/pci_ehci.h
M src/include/device/pci_mmio_cfg.h
M src/include/device/smbus.h
M src/include/elog.h
M src/include/gic.h
M src/include/memlayout.h
M src/include/option.h
M src/include/pc80/mc146818rtc.h
M src/include/reg_script.h
M src/include/rmodule.h
M src/include/rules.h
M src/include/smp/atomic.h
M src/include/smp/node.h
M src/include/smp/spinlock.h
M src/include/stddef.h
M src/include/thread.h
M src/include/timer.h
M src/include/timestamp.h
M src/include/trace.h
M src/include/watchdog.h
M src/lib/bootblock.c
M src/lib/bootmode.c
M src/lib/cbfs.c
M src/lib/cbmem_console.c
M src/lib/coreboot_table.c
M src/lib/decompressor.c
M src/lib/edid.c
M src/lib/fallback_boot.c
M src/lib/gcov-glue.c
M src/lib/hardwaremain.c
M src/lib/imd_cbmem.c
M src/lib/libgcc.c
M src/lib/malloc.c
M src/lib/prog_loaders.c
M src/lib/program.ld
M src/lib/ramtest.c
M src/lib/reg_script.c
M src/lib/reset.c
M src/lib/spd_bin.c
M src/lib/timestamp.c
M src/mainboard/advansus/a785e-i/get_bus_conf.c
M src/mainboard/advansus/a785e-i/romstage.c
M src/mainboard/amd/bettong/BiosCallOuts.c
M src/mainboard/amd/bettong/romstage.c
M src/mainboard/amd/bimini_fam10/get_bus_conf.c
M src/mainboard/amd/bimini_fam10/romstage.c
M src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c
M src/mainboard/amd/lamar/BiosCallOuts.c
M src/mainboard/amd/lamar/OemCustomize.c
M src/mainboard/amd/mahogany_fam10/get_bus_conf.c
M src/mainboard/amd/mahogany_fam10/romstage.c
M src/mainboard/amd/olivehill/BiosCallOuts.c
M src/mainboard/amd/olivehill/OemCustomize.c
M src/mainboard/amd/olivehillplus/BiosCallOuts.c
M src/mainboard/amd/parmer/BiosCallOuts.c
M src/mainboard/amd/parmer/OemCustomize.c
M src/mainboard/amd/parmer/buildOpts.c
M src/mainboard/amd/serengeti_cheetah_fam10/mptable.c
M src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
M src/mainboard/amd/thatcher/BiosCallOuts.c
M src/mainboard/amd/thatcher/buildOpts.c
M src/mainboard/amd/tilapia_fam10/get_bus_conf.c
M src/mainboard/amd/tilapia_fam10/romstage.c
M src/mainboard/amd/torpedo/Oem.h
M src/mainboard/amd/torpedo/platform_cfg.h
M src/mainboard/apple/macbook21/gpio.c
M src/mainboard/apple/macbook21/hda_verb.c
M src/mainboard/asrock/g41c-gs/acpi/ich7_pci_irqs.asl
M src/mainboard/asrock/g41c-gs/romstage.c
M src/mainboard/asrock/imb-a180/OemCustomize.c
M src/mainboard/asus/am1i-a/BiosCallOuts.c
M src/mainboard/asus/am1i-a/OemCustomize.c
M src/mainboard/asus/f2a85-m/BiosCallOuts.c
M src/mainboard/asus/f2a85-m/OemCustomize.c
M src/mainboard/asus/f2a85-m/acpi/routing.asl
M src/mainboard/asus/f2a85-m/buildOpts.c
M src/mainboard/asus/f2a85-m/romstage.c
M src/mainboard/asus/kcma-d8/acpi_tables.c
M src/mainboard/asus/kcma-d8/bootblock.c
M src/mainboard/asus/kcma-d8/mptable.c
M src/mainboard/asus/kcma-d8/romstage.c
M src/mainboard/asus/kfsn4-dre/acpi_tables.c
M src/mainboard/asus/kfsn4-dre/bootblock.c
M src/mainboard/asus/kfsn4-dre/get_bus_conf.c
M src/mainboard/asus/kfsn4-dre/romstage.c
M src/mainboard/asus/kgpe-d16/acpi_tables.c
M src/mainboard/asus/kgpe-d16/bootblock.c
M src/mainboard/asus/kgpe-d16/mptable.c
M src/mainboard/asus/kgpe-d16/romstage.c
M src/mainboard/asus/m4a78-em/get_bus_conf.c
M src/mainboard/asus/m4a78-em/romstage.c
M src/mainboard/asus/m4a785-m/get_bus_conf.c
M src/mainboard/asus/m4a785-m/romstage.c
M src/mainboard/asus/m5a88-v/get_bus_conf.c
M src/mainboard/asus/m5a88-v/romstage.c
M src/mainboard/asus/p5qpl-am/romstage.c
M src/mainboard/avalue/eax-785e/get_bus_conf.c
M src/mainboard/avalue/eax-785e/romstage.c
M src/mainboard/bap/ode_e20XX/BiosCallOuts.c
M src/mainboard/bap/ode_e20XX/OemCustomize.c
M src/mainboard/bap/ode_e21XX/BiosCallOuts.c
M src/mainboard/biostar/a68n_5200/BiosCallOuts.c
M src/mainboard/biostar/a68n_5200/OemCustomize.c
M src/mainboard/biostar/a68n_5200/romstage.c
M src/mainboard/biostar/am1ml/BiosCallOuts.c
M src/mainboard/biostar/am1ml/OemCustomize.c
M src/mainboard/cavium/cn8100_sff_evb/bootblock.c
M src/mainboard/compulab/intense_pc/gpio.c
M src/mainboard/compulab/intense_pc/romstage.c
M src/mainboard/emulation/qemu-i440fx/northbridge.c
M src/mainboard/emulation/qemu-power8/bootblock.c
M src/mainboard/foxconn/g41s-k/acpi/superio.asl
M src/mainboard/foxconn/g41s-k/hda_verb.c
M src/mainboard/foxconn/g41s-k/romstage.c
M src/mainboard/gigabyte/ma785gm/get_bus_conf.c
M src/mainboard/gigabyte/ma785gm/romstage.c
M src/mainboard/gigabyte/ma785gmt/get_bus_conf.c
M src/mainboard/gigabyte/ma785gmt/romstage.c
M src/mainboard/gigabyte/ma78gm/get_bus_conf.c
M src/mainboard/gigabyte/ma78gm/romstage.c
M src/mainboard/gizmosphere/gizmo2/BiosCallOuts.c
M src/mainboard/gizmosphere/gizmo2/OemCustomize.c
M src/mainboard/google/auron/acpi/mainboard.asl
M src/mainboard/google/auron/smihandler.c
M src/mainboard/google/auron/variants/buddy/variant.c
M src/mainboard/google/beltino/acpi_tables.c
M src/mainboard/google/beltino/lan.c
M src/mainboard/google/butterfly/mainboard.c
M src/mainboard/google/butterfly/romstage.c
M src/mainboard/google/cyan/acpi/dptf.asl
M src/mainboard/google/cyan/acpi_tables.c
M src/mainboard/google/cyan/chromeos.c
M src/mainboard/google/cyan/dsdt.asl
M src/mainboard/google/cyan/ec.c
M src/mainboard/google/cyan/romstage.c
M src/mainboard/google/cyan/smihandler.c
M src/mainboard/google/cyan/spd/spd.c
M src/mainboard/google/dragonegg/dsdt.asl
M src/mainboard/google/foster/chromeos.c
M src/mainboard/google/gale/mainboard.c
M src/mainboard/google/gale/verstage.c
M src/mainboard/google/glados/mainboard.c
M src/mainboard/google/glados/romstage.c
M src/mainboard/google/glados/smihandler.c
M src/mainboard/google/gru/board.h
M src/mainboard/google/gru/boardid.c
M src/mainboard/google/gru/bootblock.c
M src/mainboard/google/gru/chromeos.c
M src/mainboard/google/gru/mainboard.c
M src/mainboard/google/gru/pwm_regulator.c
M src/mainboard/google/gru/romstage.c
M src/mainboard/google/gru/sdram_configs.c
M src/mainboard/google/hatch/dsdt.asl
M src/mainboard/google/jecht/lan.c
M src/mainboard/google/jecht/led.c
M src/mainboard/google/jecht/romstage.c
M src/mainboard/google/jecht/smihandler.c
M src/mainboard/google/kahlee/OemCustomize.c
M src/mainboard/google/kahlee/bootblock/bootblock.c
M src/mainboard/google/kahlee/smihandler.c
M src/mainboard/google/kahlee/variants/baseboard/mainboard.c
M src/mainboard/google/kukui/boardid.c
M src/mainboard/google/kukui/romstage.c
M src/mainboard/google/link/acpi_tables.c
M src/mainboard/google/link/mainboard.c
M src/mainboard/google/link/mainboard_smi.c
M src/mainboard/google/nyan/romstage.c
M src/mainboard/google/nyan_big/romstage.c
M src/mainboard/google/nyan_blaze/romstage.c
M src/mainboard/google/oak/bootblock.c
M src/mainboard/google/oak/gpio.h
M src/mainboard/google/oak/mainboard.c
M src/mainboard/google/octopus/romstage.c
M src/mainboard/google/octopus/variants/baseboard/memory.c
M src/mainboard/google/octopus/variants/baseboard/nhlt.c
M src/mainboard/google/parrot/acpi_tables.c
M src/mainboard/google/parrot/smihandler.c
M src/mainboard/google/poppy/dsdt.asl
M src/mainboard/google/rambi/mainboard.c
M src/mainboard/google/rambi/mainboard_smi.c
M src/mainboard/google/rambi/variants/ninja/lan.c
M src/mainboard/google/rambi/variants/sumo/lan.c
M src/mainboard/google/reef/smihandler.c
M src/mainboard/google/reef/variants/baseboard/nhlt.c
M src/mainboard/google/reef/variants/snappy/mainboard.c
M src/mainboard/google/sarien/dsdt.asl
M src/mainboard/google/sarien/variants/sarien/ramstage.c
M src/mainboard/google/slippy/acpi_tables.c
M src/mainboard/google/slippy/smihandler.c
M src/mainboard/google/smaug/mainboard.c
M src/mainboard/google/storm/mainboard.c
M src/mainboard/google/stout/acpi_tables.c
M src/mainboard/google/stout/ec.c
M src/mainboard/google/urara/mainboard.c
M src/mainboard/google/veyron/boardid.c
M src/mainboard/google/veyron/bootblock.c
M src/mainboard/google/veyron_mickey/bootblock.c
M src/mainboard/google/veyron_rialto/bootblock.c
M src/mainboard/hp/abm/OemCustomize.c
M src/mainboard/hp/compaq_8200_elite_sff/mainboard.c
M src/mainboard/hp/compaq_8200_elite_sff/romstage.c
M src/mainboard/hp/dl165_g6_fam10/mptable.c
M src/mainboard/hp/dl165_g6_fam10/romstage.c
M src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c
M src/mainboard/hp/pavilion_m6_1035dx/OemCustomize.c
M src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c
M src/mainboard/iei/kino-780am2-fam10/get_bus_conf.c
M src/mainboard/iei/kino-780am2-fam10/romstage.c
M src/mainboard/intel/apollolake_rvp/romstage.c
M src/mainboard/intel/baskingridge/acpi_tables.c
M src/mainboard/intel/bayleybay_fsp/mainboard.c
M src/mainboard/intel/bayleybay_fsp/romstage.c
M src/mainboard/intel/camelbackmountain_fsp/mainboard.c
M src/mainboard/intel/cannonlake_rvp/dsdt.asl
M src/mainboard/intel/cannonlake_rvp/spd/spd_util.c
M src/mainboard/intel/cannonlake_rvp/variants/baseboard/gpio.c
M src/mainboard/intel/cannonlake_rvp/variants/baseboard/nhlt.c
M src/mainboard/intel/coffeelake_rvp/dsdt.asl
M src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c
M src/mainboard/intel/coffeelake_rvp/variants/baseboard/nhlt.c
M src/mainboard/intel/dcp847ske/acpi/superio.asl
M src/mainboard/intel/dcp847ske/early_southbridge.c
M src/mainboard/intel/dcp847ske/romstage.c
M src/mainboard/intel/galileo/gpio.c
M src/mainboard/intel/galileo/mainboard.c
M src/mainboard/intel/galileo/vboot.c
M src/mainboard/intel/glkrvp/boardid.c
M src/mainboard/intel/glkrvp/ec.c
M src/mainboard/intel/glkrvp/romstage.c
M src/mainboard/intel/glkrvp/smihandler.c
M src/mainboard/intel/glkrvp/variants/baseboard/boardid.c
M src/mainboard/intel/glkrvp/variants/baseboard/gpio.c
M src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/gpio.h
M src/mainboard/intel/glkrvp/variants/baseboard/nhlt.c
M src/mainboard/intel/harcuvar/romstage.c
M src/mainboard/intel/icelake_rvp/acpi/mainboard.asl
M src/mainboard/intel/icelake_rvp/board_id.c
M src/mainboard/intel/icelake_rvp/dsdt.asl
M src/mainboard/intel/kblrvp/acpi/ec.asl
M src/mainboard/intel/kblrvp/acpi/mainboard.asl
M src/mainboard/intel/kblrvp/chromeos.c
M src/mainboard/intel/kblrvp/dsdt.asl
M src/mainboard/intel/kblrvp/hda_verb.c
M src/mainboard/intel/kblrvp/mainboard.c
M src/mainboard/intel/kblrvp/ramstage.c
M src/mainboard/intel/kblrvp/romstage.c
M src/mainboard/intel/kblrvp/smihandler.c
M src/mainboard/intel/kunimitsu/smihandler.c
M src/mainboard/intel/strago/ec.c
M src/mainboard/intel/strago/smihandler.c
M src/mainboard/jetway/pa78vm5/get_bus_conf.c
M src/mainboard/jetway/pa78vm5/romstage.c
M src/mainboard/kontron/ktqm77/mainboard.c
M src/mainboard/lenovo/g505s/BiosCallOuts.c
M src/mainboard/lenovo/g505s/OemCustomize.c
M src/mainboard/lenovo/g505s/buildOpts.c
M src/mainboard/lenovo/s230u/romstage.c
M src/mainboard/msi/ms7721/BiosCallOuts.c
M src/mainboard/msi/ms7721/OemCustomize.c
M src/mainboard/msi/ms7721/buildOpts.c
M src/mainboard/msi/ms7721/romstage.c
M src/mainboard/msi/ms9652_fam10/get_bus_conf.c
M src/mainboard/msi/ms9652_fam10/romstage.c
M src/mainboard/ocp/monolake/mainboard.c
M src/mainboard/ocp/wedge100s/mainboard.c
M src/mainboard/ocp/wedge100s/romstage.c
M src/mainboard/opencellular/elgon/bootblock.c
M src/mainboard/pcengines/apu2/BiosCallOuts.c
M src/mainboard/pcengines/apu2/mainboard.c
M src/mainboard/pcengines/apu2/romstage.c
M src/mainboard/samsung/lumpy/acpi_tables.c
M src/mainboard/samsung/lumpy/romstage.c
M src/mainboard/samsung/stumpy/romstage.c
M src/mainboard/scaleway/tagada/bootblock.c
M src/mainboard/siemens/mc_bdx1/mainboard.c
M src/mainboard/siemens/mc_tcu3/mainboard.c
M src/mainboard/sifive/hifive-unleashed/romstage.c
M src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c
M src/mainboard/supermicro/h8dmr_fam10/romstage.c
M src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c
M src/mainboard/supermicro/h8qme_fam10/romstage.c
M src/mainboard/supermicro/h8scm_fam10/romstage.c
M src/mainboard/tyan/s2912_fam10/get_bus_conf.c
M src/mainboard/tyan/s2912_fam10/romstage.c
M src/mainboard/via/epia-m850/mainboard.c
M src/northbridge/amd/agesa/family12/northbridge.c
M src/northbridge/amd/agesa/family14/northbridge.c
M src/northbridge/amd/agesa/family15tn/northbridge.c
M src/northbridge/amd/agesa/family16kb/northbridge.c
M src/northbridge/amd/agesa/family16kb/state_machine.c
M src/northbridge/amd/agesa/state_machine.h
M src/northbridge/amd/amdfam10/debug.c
M src/northbridge/amd/amdfam10/debug.h
M src/northbridge/amd/amdfam10/early_ht.c
M src/northbridge/amd/amdfam10/link_control.c
M src/northbridge/amd/amdfam10/misc_control.c
M src/northbridge/amd/amdfam10/northbridge.c
M src/northbridge/amd/amdfam10/raminit_amdmct.c
M src/northbridge/amd/amdht/h3finit.c
M src/northbridge/amd/amdht/ht_wrapper.c
M src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
M src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
M src/northbridge/amd/amdmct/wrappers/mcti.h
M src/northbridge/amd/amdmct/wrappers/mcti_d.c
M src/northbridge/amd/pi/00630F01/northbridge.c
M src/northbridge/amd/pi/00660F01/northbridge.c
M src/northbridge/amd/pi/00730F01/northbridge.c
M src/northbridge/amd/pi/agesawrapper.c
M src/northbridge/amd/pi/agesawrapper.h
M src/northbridge/intel/e7505/raminit.c
M src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c
M src/northbridge/intel/gm45/gma.c
M src/northbridge/intel/haswell/acpi/haswell.asl
M src/northbridge/intel/haswell/gma.c
M src/northbridge/intel/haswell/northbridge.c
M src/northbridge/intel/i440bx/raminit.c
M src/northbridge/intel/i440bx/raminit.h
M src/northbridge/intel/i945/early_init.c
M src/northbridge/intel/i945/gma.c
M src/northbridge/intel/i945/raminit.c
M src/northbridge/intel/i945/raminit.h
M src/northbridge/intel/nehalem/acpi/nehalem.asl
M src/northbridge/intel/nehalem/early_init.c
M src/northbridge/intel/nehalem/gma.c
M src/northbridge/intel/nehalem/northbridge.c
M src/northbridge/intel/pineview/gma.c
M src/northbridge/intel/pineview/raminit.c
M src/northbridge/intel/sandybridge/acpi/sandybridge.asl
M src/northbridge/intel/sandybridge/early_init.c
M src/northbridge/intel/sandybridge/gma.c
M src/northbridge/intel/sandybridge/northbridge.c
M src/northbridge/intel/sandybridge/pcie.c
M src/northbridge/intel/sandybridge/raminit.c
M src/northbridge/intel/sandybridge/raminit_common.c
M src/northbridge/intel/sandybridge/raminit_mrc.c
M src/northbridge/intel/x4x/early_init.c
M src/northbridge/intel/x4x/gma.c
M src/northbridge/intel/x4x/raminit.c
M src/northbridge/intel/x4x/raminit_ddr23.c
M src/northbridge/via/vx900/lpc.c
M src/security/tpm/tspi/log.c
M src/security/tpm/tspi/tspi.c
M src/security/tpm/tss.h
M src/security/vboot/bootmode.c
M src/security/vboot/common.c
M src/security/vboot/secdata_tpm.c
M src/security/vboot/vbnv.c
M src/security/vboot/vbnv_cmos.c
M src/security/vboot/vboot_common.c
M src/security/vboot/vboot_common.h
M src/security/vboot/vboot_crtm.c
M src/security/vboot/vboot_crtm.h
M src/security/vboot/vboot_handoff.c
M src/security/vboot/vboot_loader.c
M src/security/vboot/vboot_logic.c
M src/security/vboot/verstage.c
M src/soc/amd/common/block/pi/refcode_loader.c
M src/soc/amd/common/block/psp/psp.c
M src/soc/amd/stoneyridge/BiosCallOuts.c
M src/soc/amd/stoneyridge/acpi.c
M src/soc/amd/stoneyridge/acpi/sleepstates.asl
M src/soc/amd/stoneyridge/bootblock/bootblock.c
M src/soc/amd/stoneyridge/chip.c
M src/soc/amd/stoneyridge/finalize.c
M src/soc/amd/stoneyridge/include/soc/acpi.h
M src/soc/amd/stoneyridge/include/soc/iomap.h
M src/soc/amd/stoneyridge/lpc.c
M src/soc/amd/stoneyridge/mca.c
M src/soc/amd/stoneyridge/northbridge.c
M src/soc/amd/stoneyridge/ramtop.c
M src/soc/amd/stoneyridge/romstage.c
M src/soc/amd/stoneyridge/smihandler.c
M src/soc/amd/stoneyridge/southbridge.c
M src/soc/amd/stoneyridge/spi.c
M src/soc/cavium/cn81xx/soc.c
M src/soc/cavium/common/bootblock.c
M src/soc/intel/apollolake/acpi.c
M src/soc/intel/apollolake/acpi/pci_irqs.asl
M src/soc/intel/apollolake/acpi/southbridge.asl
M src/soc/intel/apollolake/acpi/xhci.asl
M src/soc/intel/apollolake/bootblock/bootblock.c
M src/soc/intel/apollolake/chip.c
M src/soc/intel/apollolake/cpu.c
M src/soc/intel/apollolake/cse.c
M src/soc/intel/apollolake/graphics.c
M src/soc/intel/apollolake/include/soc/gpio.h
M src/soc/intel/apollolake/include/soc/pcr_ids.h
M src/soc/intel/apollolake/include/soc/pm.h
M src/soc/intel/apollolake/lpc.c
M src/soc/intel/apollolake/meminit.c
M src/soc/intel/apollolake/memmap.c
M src/soc/intel/apollolake/romstage.c
M src/soc/intel/apollolake/smihandler.c
M src/soc/intel/apollolake/uart.c
M src/soc/intel/baytrail/acpi.c
M src/soc/intel/baytrail/include/soc/pmc.h
M src/soc/intel/baytrail/include/soc/ramstage.h
M src/soc/intel/baytrail/include/soc/romstage.h
M src/soc/intel/baytrail/northcluster.c
M src/soc/intel/baytrail/romstage/raminit.c
M src/soc/intel/baytrail/romstage/romstage.c
M src/soc/intel/baytrail/smihandler.c
M src/soc/intel/baytrail/spi.c
M src/soc/intel/braswell/acpi.c
M src/soc/intel/braswell/acpi/lpc.asl
M src/soc/intel/braswell/gfx.c
M src/soc/intel/braswell/include/soc/pm.h
M src/soc/intel/braswell/memmap.c
M src/soc/intel/braswell/northcluster.c
M src/soc/intel/braswell/romstage/romstage.c
M src/soc/intel/braswell/smihandler.c
M src/soc/intel/braswell/spi.c
M src/soc/intel/broadwell/acpi.c
M src/soc/intel/broadwell/chip.c
M src/soc/intel/broadwell/finalize.c
M src/soc/intel/broadwell/igd.c
M src/soc/intel/broadwell/include/soc/ramstage.h
M src/soc/intel/broadwell/lpc.c
M src/soc/intel/broadwell/me.c
M src/soc/intel/broadwell/pcie.c
M src/soc/intel/broadwell/romstage/power_state.c
M src/soc/intel/broadwell/romstage/raminit.c
M src/soc/intel/broadwell/romstage/romstage.c
M src/soc/intel/broadwell/serialio.c
M src/soc/intel/broadwell/smihandler.c
M src/soc/intel/broadwell/spi.c
M src/soc/intel/broadwell/systemagent.c
M src/soc/intel/cannonlake/acpi.c
M src/soc/intel/cannonlake/acpi/scs.asl
M src/soc/intel/cannonlake/acpi/southbridge.asl
M src/soc/intel/cannonlake/bootblock/bootblock.c
M src/soc/intel/cannonlake/bootblock/cpu.c
M src/soc/intel/cannonlake/bootblock/pch.c
M src/soc/intel/cannonlake/chip.c
M src/soc/intel/cannonlake/chip.h
M src/soc/intel/cannonlake/cnl_memcfg_init.c
M src/soc/intel/cannonlake/cpu.c
M src/soc/intel/cannonlake/fsp_params.c
M src/soc/intel/cannonlake/graphics.c
M src/soc/intel/cannonlake/include/soc/gpio.h
M src/soc/intel/cannonlake/include/soc/pmc.h
M src/soc/intel/cannonlake/include/soc/smm.h
M src/soc/intel/cannonlake/lpc.c
M src/soc/intel/cannonlake/memmap.c
M src/soc/intel/cannonlake/romstage/fsp_params.c
M src/soc/intel/cannonlake/smihandler.c
M src/soc/intel/common/acpi/acpi_debug.asl
M src/soc/intel/common/acpi/platform.asl
M src/soc/intel/common/block/acpi/acpi.c
M src/soc/intel/common/block/cpu/car/cache_as_ram.S
M src/soc/intel/common/block/cpu/car/exit_car.S
M src/soc/intel/common/block/fast_spi/fast_spi.c
M src/soc/intel/common/block/gpio/gpio.c
M src/soc/intel/common/block/gspi/gspi.c
M src/soc/intel/common/block/hda/hda.c
M src/soc/intel/common/block/include/intelblocks/gpio_defs.h
M src/soc/intel/common/block/lpc/lpc_lib.c
M src/soc/intel/common/block/pcie/pcie.c
M src/soc/intel/common/block/pcr/pcr.c
M src/soc/intel/common/block/pmc/pmc.c
M src/soc/intel/common/block/pmc/pmclib.c
M src/soc/intel/common/block/rtc/rtc.c
M src/soc/intel/common/block/sata/sata.c
M src/soc/intel/common/block/scs/sd.c
M src/soc/intel/common/block/smbus/tco.c
M src/soc/intel/common/block/smm/smihandler.c
M src/soc/intel/common/block/smm/smm.c
M src/soc/intel/common/block/spi/spi.c
M src/soc/intel/common/block/systemagent/systemagent.c
M src/soc/intel/common/block/uart/uart.c
M src/soc/intel/common/block/xhci/xhci.c
M src/soc/intel/common/pch/lockdown/lockdown.c
M src/soc/intel/common/vbt.c
M src/soc/intel/denverton_ns/acpi.c
M src/soc/intel/denverton_ns/bootblock/bootblock.c
M src/soc/intel/denverton_ns/bootblock/uart.c
M src/soc/intel/denverton_ns/chip.c
M src/soc/intel/denverton_ns/hob_mem.c
M src/soc/intel/denverton_ns/include/soc/pmc.h
M src/soc/intel/denverton_ns/lpc.c
M src/soc/intel/denverton_ns/memmap.c
M src/soc/intel/denverton_ns/pmc.c
M src/soc/intel/denverton_ns/romstage.c
M src/soc/intel/denverton_ns/smihandler.c
M src/soc/intel/denverton_ns/uart.c
M src/soc/intel/fsp_baytrail/acpi.c
M src/soc/intel/fsp_baytrail/acpi/sleepstates.asl
M src/soc/intel/fsp_baytrail/cpu.c
M src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c
M src/soc/intel/fsp_baytrail/gpio.c
M src/soc/intel/fsp_baytrail/include/soc/pmc.h
M src/soc/intel/fsp_baytrail/include/soc/romstage.h
M src/soc/intel/fsp_baytrail/romstage/romstage.c
M src/soc/intel/fsp_baytrail/smihandler.c
M src/soc/intel/fsp_baytrail/southcluster.c
M src/soc/intel/fsp_baytrail/spi.c
M src/soc/intel/fsp_broadwell_de/chip.c
M src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c
M src/soc/intel/fsp_broadwell_de/romstage/romstage.c
M src/soc/intel/fsp_broadwell_de/southcluster.c
M src/soc/intel/icelake/acpi.c
M src/soc/intel/icelake/bootblock/bootblock.c
M src/soc/intel/icelake/bootblock/cpu.c
M src/soc/intel/icelake/bootblock/pch.c
M src/soc/intel/icelake/chip.c
M src/soc/intel/icelake/graphics.c
M src/soc/intel/icelake/include/soc/smm.h
M src/soc/intel/icelake/lpc.c
M src/soc/intel/icelake/memmap.c
M src/soc/intel/icelake/smihandler.c
M src/soc/intel/quark/bootblock/bootblock.c
M src/soc/intel/quark/bootblock/esram_init.S
M src/soc/intel/quark/i2c.c
M src/soc/intel/quark/romstage/car.c
M src/soc/intel/quark/romstage/car_stage_entry.S
M src/soc/intel/quark/romstage/fsp2_0.c
M src/soc/intel/quark/sd.c
M src/soc/intel/quark/storage_test.c
M src/soc/intel/skylake/acpi.c
M src/soc/intel/skylake/acpi/gpio.asl
M src/soc/intel/skylake/acpi/pch.asl
M src/soc/intel/skylake/acpi/scs.asl
M src/soc/intel/skylake/bootblock/bootblock.c
M src/soc/intel/skylake/bootblock/pch.c
M src/soc/intel/skylake/chip.c
M src/soc/intel/skylake/chip_fsp20.c
M src/soc/intel/skylake/cpu.c
M src/soc/intel/skylake/gpio.c
M src/soc/intel/skylake/graphics.c
M src/soc/intel/skylake/include/soc/bootblock.h
M src/soc/intel/skylake/include/soc/gpio_defs.h
M src/soc/intel/skylake/include/soc/pm.h
M src/soc/intel/skylake/include/soc/smm.h
M src/soc/intel/skylake/include/soc/vr_config.h
M src/soc/intel/skylake/me.c
M src/soc/intel/skylake/memmap.c
M src/soc/intel/skylake/romstage/car_stage.S
M src/soc/intel/skylake/romstage/romstage.c
M src/soc/intel/skylake/romstage/romstage_fsp20.c
M src/soc/intel/skylake/smihandler.c
M src/soc/intel/skylake/vr_config.c
M src/soc/mediatek/mt8173/i2c.c
M src/soc/mediatek/mt8173/include/soc/dramc_pi_api.h
M src/soc/mediatek/mt8173/memory.c
M src/soc/mediatek/mt8173/mt6391.c
M src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h
M src/soc/mediatek/mt8183/memory.c
M src/soc/nvidia/tegra210/ccplex.c
M src/soc/nvidia/tegra210/include/soc/console_uart.h
M src/soc/nvidia/tegra210/include/soc/mtc.h
M src/soc/nvidia/tegra210/romstage.c
M src/soc/nvidia/tegra210/soc.c
M src/soc/qualcomm/ipq40xx/uart.c
M src/soc/rockchip/common/gpio.c
M src/soc/rockchip/common/pwm.c
M src/soc/rockchip/rk3399/clock.c
M src/soc/rockchip/rk3399/soc.c
M src/southbridge/amd/agesa/hudson/acpi/fch.asl
M src/southbridge/amd/agesa/hudson/acpi/usb.asl
M src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h
M src/southbridge/amd/agesa/hudson/amd_pci_int_types.h
M src/southbridge/amd/agesa/hudson/fadt.c
M src/southbridge/amd/agesa/hudson/hudson.c
M src/southbridge/amd/agesa/hudson/imc.c
M src/southbridge/amd/agesa/hudson/lpc.c
M src/southbridge/amd/agesa/hudson/pci_devs.h
M src/southbridge/amd/agesa/hudson/resume.c
M src/southbridge/amd/agesa/hudson/sata.c
M src/southbridge/amd/agesa/hudson/spi.c
M src/southbridge/amd/amd8111/acpi.c
M src/southbridge/amd/amd8111/acpi/sleepstates.asl
M src/southbridge/amd/amd8111/lpc.c
M src/southbridge/amd/cimx/sb800/SBPLATFORM.h
M src/southbridge/amd/cimx/sb800/bootblock.c
M src/southbridge/amd/cimx/sb800/late.c
M src/southbridge/amd/cimx/sb800/spi.c
M src/southbridge/amd/cimx/sb900/late.c
M src/southbridge/amd/common/acpi/sleepstates.asl
M src/southbridge/amd/pi/hudson/acpi/fch.asl
M src/southbridge/amd/pi/hudson/acpi/usb.asl
M src/southbridge/amd/pi/hudson/amd_pci_int_defs.h
M src/southbridge/amd/pi/hudson/amd_pci_int_types.h
M src/southbridge/amd/pi/hudson/early_setup.c
M src/southbridge/amd/pi/hudson/fadt.c
M src/southbridge/amd/pi/hudson/gpio.h
M src/southbridge/amd/pi/hudson/hudson.c
M src/southbridge/amd/pi/hudson/hudson.h
M src/southbridge/amd/pi/hudson/lpc.c
M src/southbridge/amd/pi/hudson/pci_devs.h
M src/southbridge/amd/pi/hudson/sata.c
M src/southbridge/amd/rs780/cmn.c
M src/southbridge/amd/rs780/early_setup.c
M src/southbridge/amd/rs780/gfx.c
M src/southbridge/amd/rs780/rs780.c
M src/southbridge/amd/sb700/bootblock.c
M src/southbridge/amd/sb700/early_setup.c
M src/southbridge/amd/sb700/fadt.c
M src/southbridge/amd/sb700/lpc.c
M src/southbridge/amd/sb700/sata.c
M src/southbridge/amd/sb700/sb700.c
M src/southbridge/amd/sb700/sm.c
M src/southbridge/amd/sb700/usb.c
M src/southbridge/amd/sb800/fadt.c
M src/southbridge/amd/sb800/lpc.c
M src/southbridge/amd/sr5650/early_setup.c
M src/southbridge/amd/sr5650/ht.c
M src/southbridge/amd/sr5650/sr5650.c
M src/southbridge/intel/bd82x6x/lpc.c
M src/southbridge/intel/bd82x6x/me.c
M src/southbridge/intel/bd82x6x/me_8.x.c
M src/southbridge/intel/bd82x6x/pch.h
M src/southbridge/intel/bd82x6x/usb_ehci.c
M src/southbridge/intel/common/finalize.c
M src/southbridge/intel/common/pmutil.h
M src/southbridge/intel/common/rtc.c
M src/southbridge/intel/common/smbus.c
M src/southbridge/intel/common/smi.c
M src/southbridge/intel/common/smihandler.c
M src/southbridge/intel/common/spi.c
M src/southbridge/intel/common/usb_debug.c
M src/southbridge/intel/fsp_rangeley/acpi.c
M src/southbridge/intel/fsp_rangeley/lpc.c
M src/southbridge/intel/fsp_rangeley/romstage.c
M src/southbridge/intel/fsp_rangeley/soc.h
M src/southbridge/intel/fsp_rangeley/spi.c
M src/southbridge/intel/i82371eb/isa.c
M src/southbridge/intel/i82801gx/lpc.c
M src/southbridge/intel/i82801ix/acpi/sleepstates.asl
M src/southbridge/intel/i82801ix/i82801ix.c
M src/southbridge/intel/i82801ix/i82801ix.h
M src/southbridge/intel/i82801ix/lpc.c
M src/southbridge/intel/i82801jx/acpi/sleepstates.asl
M src/southbridge/intel/i82801jx/i82801jx.c
M src/southbridge/intel/i82801jx/lpc.c
M src/southbridge/intel/ibexpeak/lpc.c
M src/southbridge/intel/ibexpeak/me.c
M src/southbridge/intel/ibexpeak/pch.h
M src/southbridge/intel/ibexpeak/smi.c
M src/southbridge/intel/ibexpeak/smihandler.c
M src/southbridge/intel/lynxpoint/acpi/pch.asl
M src/southbridge/intel/lynxpoint/early_pch.c
M src/southbridge/intel/lynxpoint/lpc.c
M src/southbridge/intel/lynxpoint/me_9.x.c
M src/southbridge/intel/lynxpoint/pch.h
M src/southbridge/intel/lynxpoint/pmutil.c
M src/southbridge/intel/lynxpoint/smi.c
M src/southbridge/intel/lynxpoint/smihandler.c
M src/southbridge/nvidia/ck804/early_setup_car.c
M src/southbridge/nvidia/ck804/ht.c
M src/southbridge/nvidia/ck804/lpc.c
M src/southbridge/nvidia/mcp55/azalia.c
M src/southbridge/nvidia/mcp55/early_setup_car.c
M src/southbridge/nvidia/mcp55/ht.c
M src/southbridge/nvidia/mcp55/lpc.c
M src/southbridge/nvidia/mcp55/smbus.c
M src/superio/ite/common/env_ctrl.c
M src/superio/ite/common/env_ctrl.h
M src/superio/ite/common/env_ctrl_chip.h
M src/superio/ite/it8716f/superio.c
M src/superio/nuvoton/common/early_serial.c
M src/superio/nuvoton/npcd378/superio.c
M src/superio/via/vt1211/superio.c
M src/vendorcode/amd/agesa/common/agesa-entry-cfg.h
M src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mp.c
M src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc
M src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc
M src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc
M src/vendorcode/cavium/bdk/libdram/libdram.c
M src/vendorcode/cavium/include/bdk/libbdk-arch/bdk-warn.h
M src/vendorcode/google/chromeos/acpi.c
M src/vendorcode/google/chromeos/acpi/chromeos.asl
M src/vendorcode/google/chromeos/chromeos.h
M src/vendorcode/google/chromeos/cr50_enable_update.c
M src/vendorcode/google/chromeos/elog.c
M src/vendorcode/google/chromeos/ramoops.c
M src/vendorcode/google/chromeos/sar.c
M src/vendorcode/google/chromeos/tpm2.c
920 files changed, 2,285 insertions(+), 2,285 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Patrick Georgi: Looks good to me, approved