Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43760 )
Change subject: mb/clevo/kbl-u: Add Clevo N240BU as variant ......................................................................
mb/clevo/kbl-u: Add Clevo N240BU as variant
This is the board used in the Tuxedo BU1406. The ID of the graphics device differs.
Change-Id: I57dc2db78c66dd93642f41d10343d1be05fb9f17 Signed-off-by: Paul Menzel pmenzel@molgen.mpg.de --- M src/mainboard/clevo/kbl-u/Kconfig M src/mainboard/clevo/kbl-u/Kconfig.name M src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb A src/mainboard/clevo/kbl-u/variants/n240bu/data.vbt A src/mainboard/clevo/kbl-u/variants/n240bu/devicetree.cb 5 files changed, 267 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/43760/1
diff --git a/src/mainboard/clevo/kbl-u/Kconfig b/src/mainboard/clevo/kbl-u/Kconfig index a54d487..adb807a 100644 --- a/src/mainboard/clevo/kbl-u/Kconfig +++ b/src/mainboard/clevo/kbl-u/Kconfig @@ -1,4 +1,4 @@ -if BOARD_CLEVO_N130WU || BOARD_CLEVO_N131WU +if BOARD_CLEVO_N130WU || BOARD_CLEVO_N131WU || BOARD_CLEVO_N240BU
config BOARD_SPECIFIC_OPTIONS def_bool y @@ -14,6 +14,7 @@ select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM2 select NO_UART_ON_SUPERIO + select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_HDA_VERB select SOC_INTEL_KABYLAKE select SPD_READ_BY_WORD @@ -38,11 +39,13 @@ config VARIANT_DIR string default "n13xwu" if BOARD_CLEVO_N130WU || BOARD_CLEVO_N131WU + default "n240bu" if BOARD_CLEVO_N240BU
config MAINBOARD_PART_NUMBER string default "N130WU" if BOARD_CLEVO_N130WU default "N131WU" if BOARD_CLEVO_N131WU + default "N240BU" if BOARD_CLEVO_N240BU
config DEVICETREE string @@ -51,6 +54,7 @@ config CBFS_SIZE hex default 0x600000 if !VBOOT + default 0x500000 if BOARD_CLEVO_N240BU
config FMDFILE string @@ -62,7 +66,7 @@
config MAX_CPUS int - default 8 if BOARD_CLEVO_N130WU || BOARD_CLEVO_N131WU + default 8 if BOARD_CLEVO_N130WU || BOARD_CLEVO_N131WU || BOARD_CLEVO_N240BU
config DIMM_MAX int @@ -78,24 +82,22 @@
config SUBSYSTEM_DEVICE_ID hex - default 0x1313 if BOARD_CLEVO_N130WU || BOARD_CLEVO_N131WU + default 0x1313 if BOARD_CLEVO_N130WU || BOARD_CLEVO_N131WU || BOARD_CLEVO_N240BU
config VGA_BIOS_FILE string + default "pci8086,5916.rom" if BOARD_CLEVO_N240BU default "pci8086,5917.rom" if BOARD_CLEVO_N130WU || BOARD_CLEVO_N131WU
config VGA_BIOS_ID string + default "8086,5916" if BOARD_CLEVO_N240BU default "8086,5917" if BOARD_CLEVO_N130WU || BOARD_CLEVO_N131WU
config PXE_ROM_ID string default "10ec,8168"
-config FSP_M_XIP - bool - default y - config UART_FOR_CONSOLE int default 2 diff --git a/src/mainboard/clevo/kbl-u/Kconfig.name b/src/mainboard/clevo/kbl-u/Kconfig.name index f252f0b..98e0217 100644 --- a/src/mainboard/clevo/kbl-u/Kconfig.name +++ b/src/mainboard/clevo/kbl-u/Kconfig.name @@ -3,3 +3,6 @@
config BOARD_CLEVO_N131WU bool "N131WU" + +config BOARD_CLEVO_N240BU + bool "N240BU" diff --git a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb index 91252c1..ef0f938 100644 --- a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb +++ b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb @@ -213,11 +213,11 @@ device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device + device pci 08.0 off end # Gaussian Mixture Model device pci 14.0 on end # USB xHCI - device pci 14.1 off end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem device pci 16.0 off end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 + device pci 16.1 off end # Management Engine Inte2rface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT Redirection device pci 16.4 off end # Management Engine Interface 3 diff --git a/src/mainboard/clevo/kbl-u/variants/n240bu/data.vbt b/src/mainboard/clevo/kbl-u/variants/n240bu/data.vbt new file mode 100644 index 0000000..d85368b --- /dev/null +++ b/src/mainboard/clevo/kbl-u/variants/n240bu/data.vbt Binary files differ diff --git a/src/mainboard/clevo/kbl-u/variants/n240bu/devicetree.cb b/src/mainboard/clevo/kbl-u/variants/n240bu/devicetree.cb new file mode 100644 index 0000000..699211f --- /dev/null +++ b/src/mainboard/clevo/kbl-u/variants/n240bu/devicetree.cb @@ -0,0 +1,253 @@ +chip soc/intel/skylake + # Disable deep Sx states + register "deep_s3_enable_ac" = "0" + register "deep_s3_enable_dc" = "0" + register "deep_s5_enable_ac" = "0" + register "deep_s5_enable_dc" = "0" + register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" + + register "eist_enable" = "1" + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "GPP_E" + register "gpe0_dw1" = "GPP_A" + register "gpe0_dw2" = "GPP_C" + + register "gen1_dec" = "0x000c0681" + register "gen2_dec" = "0x000c1641" + register "gen3_dec" = "0x000c0081" + register "gen4_dec" = "0x00040069" + + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + + # Disable DPTF + register "dptf_enable" = "0" + + # FSP Configuration + register "ProbelessTrace" = "0" + register "EnableLan" = "0" + register "EnableSata" = "1" + register "SataSalpSupport" = "0" + register "SataMode" = "0" + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[1]" = "0" + register "SataPortsEnable[2]" = "1" + register "SataPortsDevSlp[0]" = "0" + register "SataPortsDevSlp[2]" = "0" + register "SataSpeedLimit" = "2" + register "EnableAzalia" = "1" + register "DspEnable" = "0" + register "IoBufferOwnership" = "0" + register "EnableTraceHub" = "0" + register "SsicPortEnable" = "0" + register "SmbusEnable" = "1" + register "Cio2Enable" = "0" + register "ScsEmmcEnabled" = "0" + register "ScsEmmcHs400Enabled" = "0" + register "ScsSdCardEnabled" = "0" + register "PttSwitch" = "0" + register "SkipExtGfxScan" = "1" + register "Device4Enable" = "1" + register "HeciEnabled" = "1" + register "SaGv" = "3" + register "PmConfigSlpS3MinAssert" = "2" # 50ms + register "PmConfigSlpS4MinAssert" = "1" # 1s + register "PmConfigSlpSusMinAssert" = "3" # 500ms + register "PmConfigSlpAMinAssert" = "3" # 2s + register "PmTimerDisabled" = "0" + + register "serirq_mode" = "SERIRQ_CONTINUOUS" + + register "pirqa_routing" = "PCH_IRQ11" + register "pirqb_routing" = "PCH_IRQ10" + register "pirqc_routing" = "PCH_IRQ11" + register "pirqd_routing" = "PCH_IRQ11" + register "pirqe_routing" = "PCH_IRQ11" + register "pirqf_routing" = "PCH_IRQ11" + register "pirqg_routing" = "PCH_IRQ11" + register "pirqh_routing" = "PCH_IRQ11" + + # Root port #1 x4 (TBT) + register "PcieRpEnable[0]" = "1" + register "PcieRpClkReqSupport[0]" = "1" + register "PcieRpClkReqNumber[0]" = "4" + register "PcieRpClkSrcNumber[0]" = "4" + register "PcieRpAdvancedErrorReporting[0]" = "1" + register "PcieRpLtrEnable[0]" = "1" + register "PcieRpHotPlug[0]" = "1" + + # Root port #5 x1 (LAN) + register "PcieRpEnable[4]" = "1" + register "PcieRpClkReqSupport[4]" = "1" + register "PcieRpClkReqNumber[4]" = "3" + register "PcieRpClkSrcNumber[4]" = "3" + register "PcieRpAdvancedErrorReporting[4]" = "1" + register "PcieRpLtrEnable[4]" = "1" + + # Root port #6 x1 (WLAN) + register "PcieRpEnable[5]" = "1" + register "PcieRpClkReqSupport[5]" = "1" + register "PcieRpClkReqNumber[5]" = "2" + register "PcieRpClkSrcNumber[5]" = "2" + register "PcieRpAdvancedErrorReporting[5]" = "1" + register "PcieRpLtrEnable[5]" = "1" + + # Root port #9 x4 (NVMe) + register "PcieRpEnable[8]" = "1" + register "PcieRpClkReqSupport[8]" = "1" + register "PcieRpClkReqNumber[8]" = "5" + register "PcieRpClkSrcNumber[8]" = "5" + register "PcieRpAdvancedErrorReporting[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" + + # Configure USB2 ports + register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A port right + register "usb2_ports[1]" = "USB2_PORT_FLEX(OC_SKIP)" # 3G / LTE + register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C port right + register "usb2_ports[3]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera + register "usb2_ports[4]" = "USB2_PORT_FLEX(OC_SKIP)" # Bluetooth + register "usb2_ports[5]" = "USB2_PORT_EMPTY" # NC + register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Type-A port left + register "usb2_ports[7]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C port right + register "usb2_ports[8]" = "USB2_PORT_EMPTY" # NC + register "usb2_ports[9]" = "USB2_PORT_EMPTY" # NC + + # Configure USB3 ports + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port right + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # 4G + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type C port right + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port left + + # Send an extra VR mailbox command for the PS4 exit issue + register "SendVrMbxCmd" = "2" + + # PL1 override 25W + # PL2 override 44W + register "power_limits_config" = "{ + .tdp_pl1_override = 25, + .tdp_pl2_override = 44, + }" + + # VR Settings Configuration for 4 Domains + #+----------------+-----------+-----------+-------------+----------+ + #| Domain/Setting | SA | IA | GT Unsliced | GT | + #+----------------+-----------+-----------+-------------+----------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 4A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | + #| IccMax | 5A | 64A | 31A | 31A | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + #+----------------+-----------+-----------+-------------+----------+ + register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(4), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 0, + .psi4enable = 0, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(5), + .voltage_limit = 1520, + .ac_loadline = 1030, + .dc_loadline = 1030, + }" + + register "domain_vr_config[VR_IA_CORE]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 0, + .psi4enable = 0, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(64), + .voltage_limit = 1520, + .ac_loadline = 240, + .dc_loadline = 240, + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 0, + .psi4enable = 0, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(31), + .voltage_limit = 1520, + .ac_loadline = 310, + .dc_loadline = 310, + }" + + register "domain_vr_config[VR_GT_SLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 0, + .psi4enable = 0, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(31), + .voltage_limit = 1520, + .ac_loadline = 310, + .dc_loadline = 310, + }" + + # Lock Down + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + }" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 14.0 on end # USB xHCI + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.2 on end # Thermal Subsystem + device pci 16.0 off end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 17.0 on end # SATA + device pci 1c.0 on end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 on end # PCI Express Port 5 + device pci 1c.5 on end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 on end # PCI Express Port 9 + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + end # LPC Interface + device pci 1f.1 off end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 off end # PCH SPI + device pci 1f.6 off end # GbE + end +end
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43760
to look at the new patch set (#2).
Change subject: mb/clevo/kbl-u: Add Clevo N240BU as variant ......................................................................
mb/clevo/kbl-u: Add Clevo N240BU as variant
This is the board used in the Tuxedo BU1406. The ID of the graphics device differs.
Change-Id: I57dc2db78c66dd93642f41d10343d1be05fb9f17 Signed-off-by: Paul Menzel pmenzel@molgen.mpg.de --- M src/mainboard/clevo/kbl-u/Kconfig M src/mainboard/clevo/kbl-u/Kconfig.name A src/mainboard/clevo/kbl-u/variants/n240bu/data.vbt A src/mainboard/clevo/kbl-u/variants/n240bu/devicetree.cb 4 files changed, 274 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/43760/2
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43760
to look at the new patch set (#3).
Change subject: mb/clevo/kbl-u: Add Clevo N240BU as variant ......................................................................
mb/clevo/kbl-u: Add Clevo N240BU as variant
This is the board used in the Tuxedo BU1406. The ID of the graphics device differs.
Change-Id: I57dc2db78c66dd93642f41d10343d1be05fb9f17 Signed-off-by: Paul Menzel pmenzel@molgen.mpg.de --- M src/mainboard/clevo/kbl-u/Kconfig M src/mainboard/clevo/kbl-u/Kconfig.name A src/mainboard/clevo/kbl-u/variants/n240bu/data.vbt A src/mainboard/clevo/kbl-u/variants/n240bu/devicetree.cb 4 files changed, 274 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/43760/3
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43760 )
Change subject: mb/clevo/kbl-u: Add Clevo N240BU as variant ......................................................................
Patch Set 3:
When trying to execute the VBIOS Option ROM in coreboot:
PCI ROM image, vendor ID 8086, device ID 0406, ID mismatch: vendor ID 8086, device ID 5916
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43760
to look at the new patch set (#4).
Change subject: mb/clevo/kbl-u: Add Clevo N240BU as variant ......................................................................
mb/clevo/kbl-u: Add Clevo N240BU as variant
This is the board used in the Tuxedo BU1406. The ID of the graphics device differs.
libgfxinit fails to train the eDP link, and the panel does not light up.
Extracted VBIOS Option ROM has ID 8086,0406.
coreboot is unable to run VBIOS Option ROM (even with disabled device mismatch).
Timestamp - Option ROM initialization: 77806110188 FMAP: area COREBOOT found @ 350200 (4914688 bytes) CBFS: Locating 'pci8086,5916.rom' CBFS: Found @ offset 11ce00 size 10000 In CBFS, ROM address for PCI: 00:02.0 = 0xffc6d048 PCI ROM image, vendor ID 8086, device ID 0406, ID mismatch: vendor ID 8086, device ID 5916 Copying VGA ROM Image from 0xffc6d048 to 0xc0000, 0x10000 bytes Timestamp - Option ROM copy done: 77877204844 Calling Option ROM... Unsupported software interrupt #0x15 eax 0x1905f34 Unsupported software interrupt #0x15 eax 0x5f51 Unsupported software interrupt #0x15 eax 0x5f40 Unsupported software interrupt #0x15 eax 0x5f52 Unsupported software interrupt #0x15 eax 0x5f49 Unsupported software interrupt #0x15 eax 0x3a95f49 Unsupported software interrupt #0x15 eax 0x5f14 Unsupported software interrupt #0x15 eax 0x405f35 ... Option ROM returned. VGA Option ROM was run Timestamp - Option ROM run done: 78406420234 PCI: 00:02.0 init finished in 210 msecs
1. SeaBIOS initializes the display with VBIOS Option ROM. 1. TianoCore loaded from SeaBIOS does not run. 1. Grml from USB boots. 1. SPI Flash Console works.
Change-Id: I57dc2db78c66dd93642f41d10343d1be05fb9f17 Signed-off-by: Paul Menzel pmenzel@molgen.mpg.de --- M src/mainboard/clevo/kbl-u/Kconfig M src/mainboard/clevo/kbl-u/Kconfig.name A src/mainboard/clevo/kbl-u/variants/n240bu/data.vbt A src/mainboard/clevo/kbl-u/variants/n240bu/devicetree.cb A src/mainboard/clevo/kbl-u/variants/n240bu/gma-mainboard.ads A src/mainboard/clevo/kbl-u/variants/n240bu/hda_verb.c A src/mainboard/clevo/kbl-u/variants/n240bu/include/gpio_table.h 7 files changed, 862 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/43760/4
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43760
to look at the new patch set (#6).
Change subject: mb/clevo/kbl-u: Add Clevo N240BU as variant ......................................................................
mb/clevo/kbl-u: Add Clevo N240BU as variant
This is the board used in the Tuxedo BU1406. The ID of the graphics device differs.
libgfxinit fails to train the eDP link, and the panel does not light up.
Extracted VBIOS Option ROM has ID 8086,0406.
coreboot is unable to run VBIOS Option ROM (even with disabled device mismatch).
Timestamp - Option ROM initialization: 77806110188 FMAP: area COREBOOT found @ 350200 (4914688 bytes) CBFS: Locating 'pci8086,5916.rom' CBFS: Found @ offset 11ce00 size 10000 In CBFS, ROM address for PCI: 00:02.0 = 0xffc6d048 PCI ROM image, vendor ID 8086, device ID 0406, ID mismatch: vendor ID 8086, device ID 5916 Copying VGA ROM Image from 0xffc6d048 to 0xc0000, 0x10000 bytes Timestamp - Option ROM copy done: 77877204844 Calling Option ROM... Unsupported software interrupt #0x15 eax 0x1905f34 Unsupported software interrupt #0x15 eax 0x5f51 Unsupported software interrupt #0x15 eax 0x5f40 Unsupported software interrupt #0x15 eax 0x5f52 Unsupported software interrupt #0x15 eax 0x5f49 Unsupported software interrupt #0x15 eax 0x3a95f49 Unsupported software interrupt #0x15 eax 0x5f14 Unsupported software interrupt #0x15 eax 0x405f35 ... Option ROM returned. VGA Option ROM was run Timestamp - Option ROM run done: 78406420234 PCI: 00:02.0 init finished in 210 msecs
1. SeaBIOS initializes the display with VBIOS Option ROM. 1. TianoCore loaded from SeaBIOS does not run. 1. Grml from USB boots. 1. SPI Flash Console works.
Change-Id: I57dc2db78c66dd93642f41d10343d1be05fb9f17 Signed-off-by: Paul Menzel pmenzel@molgen.mpg.de --- M src/mainboard/clevo/kbl-u/Kconfig M src/mainboard/clevo/kbl-u/Kconfig.name A src/mainboard/clevo/kbl-u/variants/n240bu/data.vbt A src/mainboard/clevo/kbl-u/variants/n240bu/devicetree.cb A src/mainboard/clevo/kbl-u/variants/n240bu/gma-mainboard.ads A src/mainboard/clevo/kbl-u/variants/n240bu/hda_verb.c A src/mainboard/clevo/kbl-u/variants/n240bu/include/gpio_table.h 7 files changed, 862 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/43760/6
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43760
to look at the new patch set (#8).
Change subject: mb/clevo/kbl-u: Add Clevo N240BU as variant ......................................................................
mb/clevo/kbl-u: Add Clevo N240BU as variant
This is the board used in the Tuxedo BU1406. The ID of the graphics device differs.
libgfxinit fails to train the eDP link, and the panel does not light up.
Extracted VBIOS Option ROM has ID 8086,0406.
coreboot is unable to run VBIOS Option ROM (even with disabled device mismatch).
Timestamp - Option ROM initialization: 77806110188 FMAP: area COREBOOT found @ 350200 (4914688 bytes) CBFS: Locating 'pci8086,5916.rom' CBFS: Found @ offset 11ce00 size 10000 In CBFS, ROM address for PCI: 00:02.0 = 0xffc6d048 PCI ROM image, vendor ID 8086, device ID 0406, ID mismatch: vendor ID 8086, device ID 5916 Copying VGA ROM Image from 0xffc6d048 to 0xc0000, 0x10000 bytes Timestamp - Option ROM copy done: 77877204844 Calling Option ROM... Unsupported software interrupt #0x15 eax 0x1905f34 Unsupported software interrupt #0x15 eax 0x5f51 Unsupported software interrupt #0x15 eax 0x5f40 Unsupported software interrupt #0x15 eax 0x5f52 Unsupported software interrupt #0x15 eax 0x5f49 Unsupported software interrupt #0x15 eax 0x3a95f49 Unsupported software interrupt #0x15 eax 0x5f14 Unsupported software interrupt #0x15 eax 0x405f35 ... Option ROM returned. VGA Option ROM was run Timestamp - Option ROM run done: 78406420234 PCI: 00:02.0 init finished in 210 msecs
1. SeaBIOS initializes the display with VBIOS Option ROM. 1. TianoCore loaded from SeaBIOS does not run. 1. Grml from USB boots. 1. SPI Flash Console works.
Change-Id: I57dc2db78c66dd93642f41d10343d1be05fb9f17 Signed-off-by: Paul Menzel pmenzel@molgen.mpg.de --- M src/mainboard/clevo/kbl-u/Kconfig M src/mainboard/clevo/kbl-u/Kconfig.name A src/mainboard/clevo/kbl-u/variants/n240bu/data.vbt A src/mainboard/clevo/kbl-u/variants/n240bu/devicetree.cb A src/mainboard/clevo/kbl-u/variants/n240bu/gma-mainboard.ads A src/mainboard/clevo/kbl-u/variants/n240bu/hda_verb.c A src/mainboard/clevo/kbl-u/variants/n240bu/include/gpio_table.h 7 files changed, 862 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/43760/8
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43760
to look at the new patch set (#9).
Change subject: mb/clevo/kbl-u: Add Clevo N240BU as variant ......................................................................
mb/clevo/kbl-u: Add Clevo N240BU as variant
This is the board used in the Tuxedo BU1406. The ID of the graphics device differs.
libgfxinit fails to train the eDP link, and the panel does not light up.
Extracted VBIOS Option ROM has ID 8086,0406.
coreboot is unable to run VBIOS Option ROM (even with disabled device mismatch).
Timestamp - Option ROM initialization: 77806110188 FMAP: area COREBOOT found @ 350200 (4914688 bytes) CBFS: Locating 'pci8086,5916.rom' CBFS: Found @ offset 11ce00 size 10000 In CBFS, ROM address for PCI: 00:02.0 = 0xffc6d048 PCI ROM image, vendor ID 8086, device ID 0406, ID mismatch: vendor ID 8086, device ID 5916 Copying VGA ROM Image from 0xffc6d048 to 0xc0000, 0x10000 bytes Timestamp - Option ROM copy done: 77877204844 Calling Option ROM... Unsupported software interrupt #0x15 eax 0x1905f34 Unsupported software interrupt #0x15 eax 0x5f51 Unsupported software interrupt #0x15 eax 0x5f40 Unsupported software interrupt #0x15 eax 0x5f52 Unsupported software interrupt #0x15 eax 0x5f49 Unsupported software interrupt #0x15 eax 0x3a95f49 Unsupported software interrupt #0x15 eax 0x5f14 Unsupported software interrupt #0x15 eax 0x405f35 ... Option ROM returned. VGA Option ROM was run Timestamp - Option ROM run done: 78406420234 PCI: 00:02.0 init finished in 210 msecs
1. SeaBIOS initializes the display with VBIOS Option ROM. 1. TianoCore loaded from SeaBIOS does not run. 1. Grml from USB boots. 1. SPI Flash Console works.
Change-Id: I57dc2db78c66dd93642f41d10343d1be05fb9f17 Signed-off-by: Paul Menzel pmenzel@molgen.mpg.de --- M src/mainboard/clevo/kbl-u/Kconfig M src/mainboard/clevo/kbl-u/Kconfig.name A src/mainboard/clevo/kbl-u/variants/n240bu/data.vbt A src/mainboard/clevo/kbl-u/variants/n240bu/devicetree.cb A src/mainboard/clevo/kbl-u/variants/n240bu/gma-mainboard.ads A src/mainboard/clevo/kbl-u/variants/n240bu/hda_verb.c A src/mainboard/clevo/kbl-u/variants/n240bu/include/gpio_table.h 7 files changed, 838 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/43760/9
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43760 )
Change subject: mb/clevo/kbl-u: Add Clevo N240BU as variant ......................................................................
Patch Set 11:
Linux currently reports the errors below:
``` $ sudo dmesg --level=err [ 0.366302] ACPI BIOS Error (bug): Could not resolve symbol [_SB.PCI0.GFX0], AE_NOT_FOUND (20190816/dswload2-159) [ 0.366374] ACPI Error: AE_NOT_FOUND, During name lookup/catalog (20190816/psobject-220) [ 4.916463] irq 11: nobody cared (try booting with the "irqpoll" option) [ 4.916537] handlers: [ 4.916554] [<000000000553a82c>] i801_isr [i2c_i801] ```
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43760 )
Change subject: mb/clevo/kbl-u: Add Clevo N240BU as variant ......................................................................
Patch Set 11:
``` […] [ 0.264326] MDS CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/mds.html for more de tails. [ 0.264326] #2 #3 […] [ 4.890293] usb 1-5: New USB device strings: Mfr=0, Product=0, SerialNumber=0 [ 4.916463] irq 11: nobody cared (try booting with the "irqpoll" option) [ 4.916506] CPU: 3 PID: 458 Comm: (imesyncd) Not tainted 5.4.0-4-amd64 #1 Debian 5.4.19-1 [ 4.916506] Hardware name: Clevo N240BU/N240BU, BIOS 4.12-1643-g1b465956c5-dirty 07/24/2020 [ 4.916507] Call Trace: [ 4.916509] <IRQ> [ 4.916514] dump_stack+0x66/0x90 [ 4.916516] __report_bad_irq+0x38/0xad [ 4.916518] note_interrupt.cold+0xb/0x6e [ 4.916520] handle_irq_event_percpu+0x72/0x80 [ 4.916521] handle_irq_event+0x3c/0x5c [ 4.916523] handle_fasteoi_irq+0xa3/0x160 [ 4.916525] do_IRQ+0x53/0xe0 [ 4.916527] common_interrupt+0xf/0xf [ 4.916528] </IRQ> [ 4.916529] RIP: 0033:0x7f94b2408ff2 [ 4.916531] Code: ff ff e9 91 c5 f4 ff 90 89 f8 31 d2 c5 c5 ef ff 09 f0 25 ff 0f 00 00 3d 80 0f 00 00 0f 8f 56 03 00 00 c5 fe 6f 0f c5 f5 74 06 <c5> fd da c1 c5 fd 74 c7 c5 fd d7 c8 85 c9 74 7e f3 0f bc d1 0f b6 [ 4.916532] RSP: 002b:00007ffdc7fa5e38 EFLAGS: 00000283 ORIG_RAX: ffffffffffffffda [ 4.916533] RAX: 00000000000007af RBX: 00007f94b2054510 RCX: 000000007eff7adf [ 4.916534] RDX: 0000000000000000 RSI: 00007f94b204f3ab RDI: 00007f94b204f48c [ 4.916535] RBP: 00007f94b204f48c R08: 0000563326e1b390 R09: 0000000000000012 [ 4.916535] R10: 00007f94b246cb80 R11: 0000000000000007 R12: 00007f94b2052d60 [ 4.916536] R13: 000000000000017b R14: 0000563326e1b260 R15: 0000563326e722e0 [ 4.916537] handlers: [ 4.916554] [<000000000553a82c>] i801_isr [i2c_i801] [ 4.916579] Disabling IRQ #11 [ 5.017483] usb 1-7: new low-speed USB device number 3 using xhci_hcd [ 5.170500] usb 1-7: New USB device found, idVendor=413c, idProduct=2106, bcdDevice= 1.01 [ 5.170502] usb 1-7: New USB device strings: Mfr=1, Product=2, SerialNumber=0 [ 5.170503] usb 1-7: Product: Dell QuietKey Keyboard [ 5.170504] usb 1-7: Manufacturer: DELL
```
Hello Felix Singer, build bot (Jenkins), Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43760
to look at the new patch set (#12).
Change subject: mb/clevo/kbl-u: Add Clevo N240BU as variant ......................................................................
mb/clevo/kbl-u: Add Clevo N240BU as variant
This is the board used in the Tuxedo BU1406. The ID of the graphics device differs.
libgfxinit fails to train the eDP link, and the panel does not light up.
Extracted VBIOS Option ROM has ID 8086,0406.
coreboot is unable to run VBIOS Option ROM (even with disabled device mismatch).
Timestamp - Option ROM initialization: 77806110188 FMAP: area COREBOOT found @ 350200 (4914688 bytes) CBFS: Locating 'pci8086,5916.rom' CBFS: Found @ offset 11ce00 size 10000 In CBFS, ROM address for PCI: 00:02.0 = 0xffc6d048 PCI ROM image, vendor ID 8086, device ID 0406, ID mismatch: vendor ID 8086, device ID 5916 Copying VGA ROM Image from 0xffc6d048 to 0xc0000, 0x10000 bytes Timestamp - Option ROM copy done: 77877204844 Calling Option ROM... Unsupported software interrupt #0x15 eax 0x1905f34 Unsupported software interrupt #0x15 eax 0x5f51 Unsupported software interrupt #0x15 eax 0x5f40 Unsupported software interrupt #0x15 eax 0x5f52 Unsupported software interrupt #0x15 eax 0x5f49 Unsupported software interrupt #0x15 eax 0x3a95f49 Unsupported software interrupt #0x15 eax 0x5f14 Unsupported software interrupt #0x15 eax 0x405f35 ... Option ROM returned. VGA Option ROM was run Timestamp - Option ROM run done: 78406420234 PCI: 00:02.0 init finished in 210 msecs
The system has the subsystem ID below:
Subsystem: CLEVO/KAPOK Computer Xeon E3-1200 v6/7th Gen Core Processor Host Bridge/DRAM Registers
1. SeaBIOS initializes the display with VBIOS Option ROM. 1. TianoCore loaded from SeaBIOS does not run. 1. Grml from USB boots. 1. SPI Flash Console works.
Change-Id: I57dc2db78c66dd93642f41d10343d1be05fb9f17 Signed-off-by: Paul Menzel pmenzel@molgen.mpg.de --- M src/mainboard/clevo/kbl-u/Kconfig M src/mainboard/clevo/kbl-u/Kconfig.name A src/mainboard/clevo/kbl-u/variants/n240bu/data.vbt A src/mainboard/clevo/kbl-u/variants/n240bu/devicetree.cb A src/mainboard/clevo/kbl-u/variants/n240bu/gma-mainboard.ads A src/mainboard/clevo/kbl-u/variants/n240bu/hda_verb.c A src/mainboard/clevo/kbl-u/variants/n240bu/include/gpio_table.h 7 files changed, 827 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/43760/12
Hello Felix Singer, build bot (Jenkins), Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43760
to look at the new patch set (#14).
Change subject: mb/clevo/kbl-u: Add Clevo N240BU as variant ......................................................................
mb/clevo/kbl-u: Add Clevo N240BU as variant
This is the board used in the Tuxedo BU1406. The ID of the graphics device differs.
libgfxinit fails to train the eDP link, and the panel does not light up.
Extracted VBIOS Option ROM has ID 8086,0406.
coreboot is unable to run VBIOS Option ROM (even with disabled device mismatch).
Timestamp - Option ROM initialization: 77806110188 FMAP: area COREBOOT found @ 350200 (4914688 bytes) CBFS: Locating 'pci8086,5916.rom' CBFS: Found @ offset 11ce00 size 10000 In CBFS, ROM address for PCI: 00:02.0 = 0xffc6d048 PCI ROM image, vendor ID 8086, device ID 0406, ID mismatch: vendor ID 8086, device ID 5916 Copying VGA ROM Image from 0xffc6d048 to 0xc0000, 0x10000 bytes Timestamp - Option ROM copy done: 77877204844 Calling Option ROM... Unsupported software interrupt #0x15 eax 0x1905f34 Unsupported software interrupt #0x15 eax 0x5f51 Unsupported software interrupt #0x15 eax 0x5f40 Unsupported software interrupt #0x15 eax 0x5f52 Unsupported software interrupt #0x15 eax 0x5f49 Unsupported software interrupt #0x15 eax 0x3a95f49 Unsupported software interrupt #0x15 eax 0x5f14 Unsupported software interrupt #0x15 eax 0x405f35 ... Option ROM returned. VGA Option ROM was run Timestamp - Option ROM run done: 78406420234 PCI: 00:02.0 init finished in 210 msecs
The system has the subsystem ID below:
Subsystem: CLEVO/KAPOK Computer Xeon E3-1200 v6/7th Gen Core Processor Host Bridge/DRAM Registers
1. SeaBIOS initializes the display with VBIOS Option ROM. 1. TianoCore loaded from SeaBIOS does not run. 1. Grml from USB boots. 1. SPI Flash Console works.
Change-Id: I57dc2db78c66dd93642f41d10343d1be05fb9f17 Signed-off-by: Paul Menzel pmenzel@molgen.mpg.de --- M src/mainboard/clevo/kbl-u/Kconfig M src/mainboard/clevo/kbl-u/Kconfig.name M src/mainboard/clevo/kbl-u/devicetree.cb A src/mainboard/clevo/kbl-u/variants/n240bu/data.vbt A src/mainboard/clevo/kbl-u/variants/n240bu/gma-mainboard.ads A src/mainboard/clevo/kbl-u/variants/n240bu/hda_verb.c A src/mainboard/clevo/kbl-u/variants/n240bu/include/gpio_table.h A src/mainboard/clevo/kbl-u/variants/n240bu/overridetree.cb 8 files changed, 589 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/43760/14
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43760 )
Change subject: mb/clevo/kbl-u: Add Clevo N240BU as variant ......................................................................
Patch Set 14:
After converting to override tree, I am now getting [1]:
mainboard_silicon_init_params: End functionBUG: p2sb_set_hide_bit requests hidden 00:1f.1 PCI: dev is NULL!
[1]: https://paste.debian.net/1157924/
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43760 )
Change subject: mb/clevo/kbl-u: Add Clevo N240BU as variant ......................................................................
Patch Set 14:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43760/14/src/mainboard/clevo/kbl-u/... File src/mainboard/clevo/kbl-u/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/43760/14/src/mainboard/clevo/kbl-u/... PS14, Line 191: register "serirq_mode" = "SERIRQ_CONTINUOUS" you can drop that; serirq is only used for ec, which can make use of quiet mode and thus save power
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43760 )
Change subject: mb/clevo/kbl-u: Add Clevo N240BU as variant ......................................................................
Patch Set 14:
(3 comments)
https://review.coreboot.org/c/coreboot/+/43760/14/src/mainboard/clevo/kbl-u/... File src/mainboard/clevo/kbl-u/Kconfig:
https://review.coreboot.org/c/coreboot/+/43760/14/src/mainboard/clevo/kbl-u/... PS14, Line 3: if BOARD_CLEVO_N13xWU || BOARD_CLEVO_N240BU let's go for a baseboard approch, because this will get way too long. see x11-lga1151-series
https://review.coreboot.org/c/coreboot/+/43760/14/src/mainboard/clevo/kbl-u/... PS14, Line 54: default 8 if BOARD_CLEVO_N13xWU || BOARD_CLEVO_N240BU we need a different solution here, this list will get veeeeeeeeery looooong
https://review.coreboot.org/c/coreboot/+/43760/14/src/mainboard/clevo/kbl-u/... File src/mainboard/clevo/kbl-u/variants/n240bu/include/gpio_table.h:
https://review.coreboot.org/c/coreboot/+/43760/14/src/mainboard/clevo/kbl-u/... PS14, Line 2: use maxim's intelp2m tool to convert this and verify it with schematics, please. example: https://review.coreboot.org/c/coreboot/+/43652/19..20/src/mainboard/system76...
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43760 )
Change subject: mb/clevo/kbl-u: Add Clevo N240BU as variant ......................................................................
Patch Set 14:
(4 comments)
https://review.coreboot.org/c/coreboot/+/43760/14/src/mainboard/clevo/kbl-u/... File src/mainboard/clevo/kbl-u/Kconfig:
https://review.coreboot.org/c/coreboot/+/43760/14/src/mainboard/clevo/kbl-u/... PS14, Line 3: if BOARD_CLEVO_N13xWU || BOARD_CLEVO_N240BU
let's go for a baseboard approch, because this will get way too long. […]
"baseboard approach" basically means using a new Kconfig symbol that is selected by both variants.
Step 1: Move this if-clause after what currently is `BOARD_SPECIFIC_OPTIONS`
https://review.coreboot.org/c/coreboot/+/43760/14/src/mainboard/clevo/kbl-u/... PS14, Line 5: BOARD_SPECIFIC_OPTIONS Step 2: Replace this with, e.g., `BOARD_CLEVO_KBL_U_SERIES`
https://review.coreboot.org/c/coreboot/+/43760/14/src/mainboard/clevo/kbl-u/... PS14, Line 6: def_bool y Step 3: Make the new symbol default to n
https://review.coreboot.org/c/coreboot/+/43760/14/src/mainboard/clevo/kbl-u/... File src/mainboard/clevo/kbl-u/variants/n240bu/include/gpio_table.h:
https://review.coreboot.org/c/coreboot/+/43760/14/src/mainboard/clevo/kbl-u/... PS14, Line 31: // PIRQA# There's a G-sensor there, maybe that's why you're having problems with IRQ11
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43760 )
Change subject: mb/clevo/kbl-u: Add Clevo N240BU as variant ......................................................................
Patch Set 14:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43760/14/src/mainboard/clevo/kbl-u/... File src/mainboard/clevo/kbl-u/variants/n240bu/include/gpio_table.h:
https://review.coreboot.org/c/coreboot/+/43760/14/src/mainboard/clevo/kbl-u/... PS14, Line 31: // PIRQA#
There's a G-sensor there, maybe that's why you're having problems with IRQ11
Wait, this pin isn't wired as native function with the current config...
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43760 )
Change subject: mb/clevo/kbl-u: Add Clevo N240BU as variant ......................................................................
Patch Set 14:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43760/14/src/mainboard/clevo/kbl-u/... File src/mainboard/clevo/kbl-u/Kconfig:
https://review.coreboot.org/c/coreboot/+/43760/14/src/mainboard/clevo/kbl-u/... PS14, Line 54: default 8 if BOARD_CLEVO_N13xWU || BOARD_CLEVO_N240BU
we need a different solution here, this list will get veeeeeeeeery looooong
Can’t we always default to 8?
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43760 )
Change subject: mb/clevo/kbl-u: Add Clevo N240BU as variant ......................................................................
Patch Set 15:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43760/15/src/mainboard/clevo/kbl-u/... File src/mainboard/clevo/kbl-u/Kconfig:
https://review.coreboot.org/c/coreboot/+/43760/15/src/mainboard/clevo/kbl-u/... PS15, Line 48: default 0x500000 if BOARD_CLEVO_N240BU Starting with no configuration, selecting the variant, the 5 MB value is not chosen. I guess, this line needs to be before the other default line.
Hello Felix Singer, build bot (Jenkins), Angel Pons, Michael Niewöhner,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43760
to look at the new patch set (#16).
Change subject: mb/clevo/kbl-u: Add Clevo N240BU as variant ......................................................................
mb/clevo/kbl-u: Add Clevo N240BU as variant
This is the board used in the Tuxedo BU1406. The ID of the graphics device differs.
libgfxinit fails to train the eDP link, and the panel does not light up.
Extracted VBIOS Option ROM has ID 8086,0406.
coreboot is unable to run VBIOS Option ROM (even with disabled device mismatch).
Timestamp - Option ROM initialization: 77806110188 FMAP: area COREBOOT found @ 350200 (4914688 bytes) CBFS: Locating 'pci8086,5916.rom' CBFS: Found @ offset 11ce00 size 10000 In CBFS, ROM address for PCI: 00:02.0 = 0xffc6d048 PCI ROM image, vendor ID 8086, device ID 0406, ID mismatch: vendor ID 8086, device ID 5916 Copying VGA ROM Image from 0xffc6d048 to 0xc0000, 0x10000 bytes Timestamp - Option ROM copy done: 77877204844 Calling Option ROM... Unsupported software interrupt #0x15 eax 0x1905f34 Unsupported software interrupt #0x15 eax 0x5f51 Unsupported software interrupt #0x15 eax 0x5f40 Unsupported software interrupt #0x15 eax 0x5f52 Unsupported software interrupt #0x15 eax 0x5f49 Unsupported software interrupt #0x15 eax 0x3a95f49 Unsupported software interrupt #0x15 eax 0x5f14 Unsupported software interrupt #0x15 eax 0x405f35 ... Option ROM returned. VGA Option ROM was run Timestamp - Option ROM run done: 78406420234 PCI: 00:02.0 init finished in 210 msecs
The system has the subsystem ID below:
Subsystem: CLEVO/KAPOK Computer Xeon E3-1200 v6/7th Gen Core Processor Host Bridge/DRAM Registers
1. SeaBIOS initializes the display with VBIOS Option ROM. 1. TianoCore loaded from SeaBIOS does not run. 1. Grml from USB boots. 1. SPI Flash Console works.
Change-Id: I57dc2db78c66dd93642f41d10343d1be05fb9f17 Signed-off-by: Paul Menzel pmenzel@molgen.mpg.de --- M src/mainboard/clevo/kbl-u/Kconfig M src/mainboard/clevo/kbl-u/Kconfig.name A src/mainboard/clevo/kbl-u/variants/n240bu/data.vbt A src/mainboard/clevo/kbl-u/variants/n240bu/gma-mainboard.ads A src/mainboard/clevo/kbl-u/variants/n240bu/hda_verb.c A src/mainboard/clevo/kbl-u/variants/n240bu/include/gpio_table.h A src/mainboard/clevo/kbl-u/variants/n240bu/overridetree.cb 7 files changed, 588 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/43760/16
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43760 )
Change subject: mb/clevo/kbl-u: Add Clevo N240BU as variant ......................................................................
Patch Set 16:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43760/14/src/mainboard/clevo/kbl-u/... File src/mainboard/clevo/kbl-u/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/43760/14/src/mainboard/clevo/kbl-u/... PS14, Line 191: register "serirq_mode" = "SERIRQ_CONTINUOUS"
you can drop that; serirq is only used for ec, which can make use of quiet mode and thus save power
After removing that, keyboard and mouse didn’t work anymore in Debian GNU/Linux.
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43760 )
Change subject: mb/clevo/kbl-u: Add Clevo N240BU as variant ......................................................................
Patch Set 16:
(3 comments)
https://review.coreboot.org/c/coreboot/+/43760/16//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/43760/16//COMMIT_MSG@6 PS16, Line 6: : mb/clevo/kbl-u: Add Clevo N240BU as variant : : This is the board used in the Tuxedo BU1406. The ID of the graphics device : differs. so, we should make the BU1406 an OEM variant - Felix and me are looking into Kconfig in the next days to find the best way for this.
Further, I realized N2xxXU all use the same board. These are the differences: - N25XBU has an additional SATA breakout board - N2xxWU have a KBL-R soc
-> we can support them all with the N240BU baseboard
https://review.coreboot.org/c/coreboot/+/43760/14/src/mainboard/clevo/kbl-u/... File src/mainboard/clevo/kbl-u/Kconfig:
https://review.coreboot.org/c/coreboot/+/43760/14/src/mainboard/clevo/kbl-u/... PS14, Line 54: default 8 if BOARD_CLEVO_N13xWU || BOARD_CLEVO_N240BU
Can’t we always default to 8?
should be ok, yes
https://review.coreboot.org/c/coreboot/+/43760/14/src/mainboard/clevo/kbl-u/... File src/mainboard/clevo/kbl-u/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/43760/14/src/mainboard/clevo/kbl-u/... PS14, Line 191: register "serirq_mode" = "SERIRQ_CONTINUOUS"
After removing that, keyboard and mouse didn’t work anymore in Debian GNU/Linux.
damn, I checked the wrong schematics. sry for confusion. SERIRQ is used by EC and TPM. When keyboard stops working, I assume this specific ec does not support quiet mode. I couldn't find info on SERIRQ for SLB9665TT TPM.
Long story short: let's leave that as-is
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43760 )
Change subject: mb/clevo/kbl-u: Add Clevo N240BU as variant ......................................................................
Patch Set 16:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43760/16//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/43760/16//COMMIT_MSG@6 PS16, Line 6: : mb/clevo/kbl-u: Add Clevo N240BU as variant : : This is the board used in the Tuxedo BU1406. The ID of the graphics device : differs.
so, we should make the BU1406 an OEM variant - Felix and me are looking into Kconfig in the next day […]
If you send me those models, I can take care of testing the ports for them.
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43760 )
Change subject: mb/clevo/kbl-u: Add Clevo N240BU as variant ......................................................................
Patch Set 16:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43760/15/src/mainboard/clevo/kbl-u/... File src/mainboard/clevo/kbl-u/Kconfig:
https://review.coreboot.org/c/coreboot/+/43760/15/src/mainboard/clevo/kbl-u/... PS15, Line 48: default 0x500000 if BOARD_CLEVO_N240BU
Starting with no configuration, selecting the variant, the 5 MB value is not chosen. […]
we will need sth like that: config CBFS_SIZE default 0x600000 if BOARD_CLEVO_N240BU && VBOOT default 0x500000 if BOARD_CLEVO_N240BU && !VBOOT ...
or this: if VBOOT config CBFS_SIZE default 0x500000 if BOARD_CLEVO_N240BU default 0x500000 if ... ... else config CBFS_SIZE default 0x500000 if BOARD_CLEVO_N240BU default 0x500000 if ... ... endif
I first want to make sure the cbfs sizes really differ, before making it that complex. I wouldn't be surprised if all kbl devices (or even all current clevo devices) have the same size.
Hello Felix Singer, build bot (Jenkins), Angel Pons, Michael Niewöhner,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43760
to look at the new patch set (#17).
Change subject: mb/clevo/kbl-u: Add Clevo N240BU as variant ......................................................................
mb/clevo/kbl-u: Add Clevo N240BU as variant
This is the board used in the Tuxedo BU1406. The ID of the graphics device differs.
libgfxinit fails to train the eDP link, and the panel does not light up.
Extracted VBIOS Option ROM has ID 8086,0406.
coreboot is unable to run VBIOS Option ROM (even with disabled device mismatch).
Timestamp - Option ROM initialization: 77806110188 FMAP: area COREBOOT found @ 350200 (4914688 bytes) CBFS: Locating 'pci8086,5916.rom' CBFS: Found @ offset 11ce00 size 10000 In CBFS, ROM address for PCI: 00:02.0 = 0xffc6d048 PCI ROM image, vendor ID 8086, device ID 0406, ID mismatch: vendor ID 8086, device ID 5916 Copying VGA ROM Image from 0xffc6d048 to 0xc0000, 0x10000 bytes Timestamp - Option ROM copy done: 77877204844 Calling Option ROM... Unsupported software interrupt #0x15 eax 0x1905f34 Unsupported software interrupt #0x15 eax 0x5f51 Unsupported software interrupt #0x15 eax 0x5f40 Unsupported software interrupt #0x15 eax 0x5f52 Unsupported software interrupt #0x15 eax 0x5f49 Unsupported software interrupt #0x15 eax 0x3a95f49 Unsupported software interrupt #0x15 eax 0x5f14 Unsupported software interrupt #0x15 eax 0x405f35 ... Option ROM returned. VGA Option ROM was run Timestamp - Option ROM run done: 78406420234 PCI: 00:02.0 init finished in 210 msecs
The system has the subsystem ID below:
Subsystem: CLEVO/KAPOK Computer Xeon E3-1200 v6/7th Gen Core Processor Host Bridge/DRAM Registers
1. SeaBIOS initializes the display with VBIOS Option ROM. 1. TianoCore loaded from SeaBIOS does not run. 1. Grml from USB boots. 1. SPI Flash Console works.
Change-Id: I57dc2db78c66dd93642f41d10343d1be05fb9f17 Signed-off-by: Paul Menzel pmenzel@molgen.mpg.de --- M src/mainboard/clevo/kbl-u/Kconfig M src/mainboard/clevo/kbl-u/Kconfig.name A src/mainboard/clevo/kbl-u/variants/n240bu/data.vbt A src/mainboard/clevo/kbl-u/variants/n240bu/gma-mainboard.ads A src/mainboard/clevo/kbl-u/variants/n240bu/hda_verb.c A src/mainboard/clevo/kbl-u/variants/n240bu/include/gpio_table.h A src/mainboard/clevo/kbl-u/variants/n240bu/overridetree.cb 7 files changed, 587 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/43760/17
Hello Felix Singer, build bot (Jenkins), Angel Pons, Michael Niewöhner,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43760
to look at the new patch set (#19).
Change subject: mb/clevo/kbl-u: Add Clevo N240BU as variant ......................................................................
mb/clevo/kbl-u: Add Clevo N240BU as variant
This is the white label device also sold as TUXEDO Book BU1406.
Extracted Video BIOS Option ROM has ID 8086,0406, but the ID of the graphics device differs, but will be mapped to the correct ID.
The system has the subsystem ID below:
Subsystem: CLEVO/KAPOK Computer Xeon E3-1200 v6/7th Gen Core Processor Host Bridge/DRAM Registers
1. SeaBIOS rel-1.14.0-14-g748d619 initializes the display with VBIOS Option ROM. 2. Using GOP for graphics initialization works. 3. Grml 2020.06 on USB flash drive boots. 4. SPI Flash Console works. 5. Debian Sid/unstable with Linux 5.9.6 boots from the NVMe SSD. 6. ACPI S3 resume/suspend works (`freeze`)
Not working:
1. Function keys (EC ACPI missing) 2. Webcam
Change-Id: I57dc2db78c66dd93642f41d10343d1be05fb9f17 Signed-off-by: Paul Menzel pmenzel@molgen.mpg.de --- M src/mainboard/clevo/kbl-u/Kconfig M src/mainboard/clevo/kbl-u/Kconfig.name A src/mainboard/clevo/kbl-u/variants/n240bu/data.vbt A src/mainboard/clevo/kbl-u/variants/n240bu/gma-mainboard.ads A src/mainboard/clevo/kbl-u/variants/n240bu/hda_verb.c A src/mainboard/clevo/kbl-u/variants/n240bu/include/gpio_table.h A src/mainboard/clevo/kbl-u/variants/n240bu/overridetree.cb 7 files changed, 587 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/43760/19
Hello Felix Singer, build bot (Jenkins), Angel Pons, Michael Niewöhner,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43760
to look at the new patch set (#20).
Change subject: mb/clevo/kbl-u: Add Clevo N240BU as variant ......................................................................
mb/clevo/kbl-u: Add Clevo N240BU as variant
This is the white label device also sold as TUXEDO Book BU1406.
Extracted Video BIOS Option ROM has ID 8086,0406, but the ID of the graphics device differs, but will be mapped to the correct ID.
The system has the subsystem ID below:
Subsystem: CLEVO/KAPOK Computer Xeon E3-1200 v6/7th Gen Core Processor Host Bridge/DRAM Registers
1. SeaBIOS rel-1.14.0-14-g748d619 initializes the display with VBIOS Option ROM. 2. Using GOP for graphics initialization works. 3. Grml 2020.06 on USB flash drive boots. 4. SPI Flash Console works. 5. Debian Sid/unstable with Linux 5.9.6 boots from the NVMe SSD. 6. ACPI S3 resume/suspend works (`freeze`)
Not working:
1. Function keys (EC ACPI missing) 2. Webcam
Change-Id: I57dc2db78c66dd93642f41d10343d1be05fb9f17 Signed-off-by: Paul Menzel pmenzel@molgen.mpg.de --- M src/mainboard/clevo/kbl-u/Kconfig M src/mainboard/clevo/kbl-u/Kconfig.name A src/mainboard/clevo/kbl-u/variants/n240bu/board_info.txt A src/mainboard/clevo/kbl-u/variants/n240bu/data.vbt A src/mainboard/clevo/kbl-u/variants/n240bu/gma-mainboard.ads A src/mainboard/clevo/kbl-u/variants/n240bu/gpios.c A src/mainboard/clevo/kbl-u/variants/n240bu/gpios_early.c A src/mainboard/clevo/kbl-u/variants/n240bu/hda_verb.c A src/mainboard/clevo/kbl-u/variants/n240bu/include/gpio_table.h A src/mainboard/clevo/kbl-u/variants/n240bu/overridetree.cb 10 files changed, 1,107 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/43760/20
Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43760 )
Change subject: mb/clevo/kbl-u: Add Clevo N240BU as variant ......................................................................
Patch Set 20: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/43760/20/src/mainboard/clevo/kbl-u/... File src/mainboard/clevo/kbl-u/variants/n240bu/include/gpio_table.h:
PS20: Remove this
Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43760 )
Change subject: mb/clevo/kbl-u: Add Clevo N240BU as variant ......................................................................
Patch Set 20:
(2 comments)
https://review.coreboot.org/c/coreboot/+/43760/20//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/43760/20//COMMIT_MSG@29 PS20, Line 29: 2. Webcam Please recheck the USB port configuration in devicetree. According to schematics camera uses USB port 6 instead of 4.
https://review.coreboot.org/c/coreboot/+/43760/20/src/mainboard/clevo/kbl-u/... File src/mainboard/clevo/kbl-u/variants/n240bu/overridetree.cb:
PS20: Please copy the devicetree from N130WU and do you changes there. I will sort out the differences in a seperate patch.
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43760 )
Change subject: mb/clevo/kbl-u: Add Clevo N240BU as variant ......................................................................
Patch Set 20:
Linux logs:
i915 0000:00:02.0: [drm] Panel advertises DPCD backlight support, but VBT disagrees. If your backlight controls don't work try booting with i915.enable_dpcd_backlight=1. If your machine needs this, please file a _new_ bug report on drm/i915, see https://gitlab.freedesktop.org/drm/intel/-/wikis/How-to-file-i915-bugs for details.
Hello Felix Singer, build bot (Jenkins), Angel Pons, Michael Niewöhner,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43760
to look at the new patch set (#21).
Change subject: mb/clevo/kbl-u: Add Clevo N240BU as variant ......................................................................
mb/clevo/kbl-u: Add Clevo N240BU as variant
This is the white label device also sold as TUXEDO Book BU1406.
Extracted Video BIOS Option ROM has ID 8086,0406, but the ID of the graphics device differs, but will be mapped to the correct ID.
The system has the subsystem ID below:
Subsystem: CLEVO/KAPOK Computer Xeon E3-1200 v6/7th Gen Core Processor Host Bridge/DRAM Registers
1. SeaBIOS rel-1.14.0-14-g748d619 initializes the display with VBIOS Option ROM. 2. Using GOP for graphics initialization works. 3. Grml 2020.06 on USB flash drive boots. 4. SPI Flash Console works. 5. Debian Sid/unstable with Linux 5.9.6 boots from the NVMe SSD. 6. ACPI S3 resume/suspend works (`freeze`)
Just copy the devicetree from the Clevo N130WU, and adapt it in followups.
Not working:
1. Function keys (EC ACPI missing) 2. Webcam
Change-Id: I57dc2db78c66dd93642f41d10343d1be05fb9f17 Signed-off-by: Paul Menzel pmenzel@molgen.mpg.de --- M src/mainboard/clevo/kbl-u/Kconfig M src/mainboard/clevo/kbl-u/Kconfig.name D src/mainboard/clevo/kbl-u/include/mainboard/gpio.h A src/mainboard/clevo/kbl-u/variants/n240bu/board_info.txt A src/mainboard/clevo/kbl-u/variants/n240bu/data.vbt A src/mainboard/clevo/kbl-u/variants/n240bu/devicetree.cb A src/mainboard/clevo/kbl-u/variants/n240bu/gma-mainboard.ads A src/mainboard/clevo/kbl-u/variants/n240bu/gpios.c A src/mainboard/clevo/kbl-u/variants/n240bu/gpios_early.c A src/mainboard/clevo/kbl-u/variants/n240bu/hda_verb.c A src/mainboard/clevo/kbl-u/variants/n240bu/include/gpio_table.h 11 files changed, 1,261 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/43760/21
Hello Felix Singer, build bot (Jenkins), Angel Pons, Michael Niewöhner,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43760
to look at the new patch set (#22).
Change subject: mb/clevo/kbl-u: Add Clevo N240BU as variant ......................................................................
mb/clevo/kbl-u: Add Clevo N240BU as variant
This is the white label device also sold as TUXEDO Book BU1406.
Extracted Video BIOS Option ROM has ID 8086,0406, but the ID of the graphics device differs, but will be mapped to the correct ID.
The system has the subsystem ID below:
Subsystem: CLEVO/KAPOK Computer Xeon E3-1200 v6/7th Gen Core Processor Host Bridge/DRAM Registers
1. SeaBIOS rel-1.14.0-14-g748d619 initializes the display with VBIOS Option ROM. 2. Using GOP for graphics initialization works. 3. Grml 2020.06 on USB flash drive boots. 4. SPI Flash Console works. 5. Debian Sid/unstable with Linux 5.9.6 boots from the NVMe SSD. 6. ACPI S3 resume/suspend works (`freeze`)
Just copy the devicetree from the Clevo N130WU, and adapt it in followups.
Not working:
1. Function keys (EC ACPI missing) 2. Webcam
Change-Id: I57dc2db78c66dd93642f41d10343d1be05fb9f17 Signed-off-by: Paul Menzel pmenzel@molgen.mpg.de --- M src/mainboard/clevo/kbl-u/Kconfig M src/mainboard/clevo/kbl-u/Kconfig.name A src/mainboard/clevo/kbl-u/variants/n240bu/board_info.txt A src/mainboard/clevo/kbl-u/variants/n240bu/data.vbt A src/mainboard/clevo/kbl-u/variants/n240bu/devicetree.cb A src/mainboard/clevo/kbl-u/variants/n240bu/gma-mainboard.ads A src/mainboard/clevo/kbl-u/variants/n240bu/gpios.c A src/mainboard/clevo/kbl-u/variants/n240bu/gpios_early.c A src/mainboard/clevo/kbl-u/variants/n240bu/hda_verb.c 9 files changed, 750 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/43760/22
Felix Singer has uploaded a new patch set (#23) to the change originally created by Paul Menzel. ( https://review.coreboot.org/c/coreboot/+/43760 )
Change subject: mb/clevo/kbl-u: Add Clevo N240BU as variant ......................................................................
mb/clevo/kbl-u: Add Clevo N240BU as variant
This is the white label device also sold as TUXEDO Book BU1406.
Extracted Video BIOS Option ROM has ID 8086,0406, but the ID of the graphics device differs, but will be mapped to the correct ID.
The system has the subsystem ID below:
Subsystem: CLEVO/KAPOK Computer Xeon E3-1200 v6/7th Gen Core Processor Host Bridge/DRAM Registers
1. SeaBIOS rel-1.14.0-14-g748d619 initializes the display with VBIOS Option ROM. 2. Using GOP for graphics initialization works. 3. Grml 2020.06 on USB flash drive boots. 4. SPI Flash Console works. 5. Debian Sid/unstable with Linux 5.9.6 boots from the NVMe SSD. 6. ACPI S3 resume/suspend works (`freeze`)
Just copy the devicetree from the Clevo N130WU, and adapt it in followups.
Not working:
1. Function keys (EC ACPI missing) 2. Webcam
Change-Id: I57dc2db78c66dd93642f41d10343d1be05fb9f17 Signed-off-by: Paul Menzel pmenzel@molgen.mpg.de --- M src/mainboard/clevo/kbl-u/Kconfig M src/mainboard/clevo/kbl-u/Kconfig.name A src/mainboard/clevo/kbl-u/variants/n240bu/board_info.txt A src/mainboard/clevo/kbl-u/variants/n240bu/data.vbt A src/mainboard/clevo/kbl-u/variants/n240bu/devicetree.cb A src/mainboard/clevo/kbl-u/variants/n240bu/gma-mainboard.ads A src/mainboard/clevo/kbl-u/variants/n240bu/gpio.c A src/mainboard/clevo/kbl-u/variants/n240bu/gpio_early.c A src/mainboard/clevo/kbl-u/variants/n240bu/hda_verb.c 9 files changed, 750 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/43760/23
Felix Singer has uploaded a new patch set (#24) to the change originally created by Paul Menzel. ( https://review.coreboot.org/c/coreboot/+/43760 )
Change subject: mb/clevo/kbl-u: Add Clevo N240BU as variant ......................................................................
mb/clevo/kbl-u: Add Clevo N240BU as variant
This is the white label device also sold as TUXEDO Book BU1406.
Extracted Video BIOS Option ROM has ID 8086,0406, but the ID of the graphics device differs, but will be mapped to the correct ID.
The system has the subsystem ID below:
Subsystem: CLEVO/KAPOK Computer Xeon E3-1200 v6/7th Gen Core Processor Host Bridge/DRAM Registers
1. SeaBIOS rel-1.14.0-14-g748d619 initializes the display with VBIOS Option ROM. 2. Using GOP for graphics initialization works. 3. Grml 2020.06 on USB flash drive boots. 4. SPI Flash Console works. 5. Debian Sid/unstable with Linux 5.9.6 boots from the NVMe SSD. 6. ACPI S3 resume/suspend works (`freeze`)
Just copy the devicetree from the Clevo N130WU, and adapt it in followups.
Not working:
1. Function keys (EC ACPI missing) 2. Webcam
Change-Id: I57dc2db78c66dd93642f41d10343d1be05fb9f17 Signed-off-by: Paul Menzel pmenzel@molgen.mpg.de --- M src/mainboard/clevo/kbl-u/Kconfig M src/mainboard/clevo/kbl-u/Kconfig.name A src/mainboard/clevo/kbl-u/variants/n240bu/board_info.txt A src/mainboard/clevo/kbl-u/variants/n240bu/data.vbt A src/mainboard/clevo/kbl-u/variants/n240bu/devicetree.cb A src/mainboard/clevo/kbl-u/variants/n240bu/gma-mainboard.ads A src/mainboard/clevo/kbl-u/variants/n240bu/gpio.c A src/mainboard/clevo/kbl-u/variants/n240bu/gpio_early.c A src/mainboard/clevo/kbl-u/variants/n240bu/hda_verb.c 9 files changed, 747 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/43760/24
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43760 )
Change subject: mb/clevo/kbl-u: Add Clevo N240BU as variant ......................................................................
Patch Set 24:
(2 comments)
Reason for build failure of patch set 24:
SCONFIG mainboard/clevo/kbl-u/variants/n240bu/devicetree.cb ERROR: duplicate 'register' key 'PcieRpClkReqSupport[1]'.
https://review.coreboot.org/c/coreboot/+/43760/20//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/43760/20//COMMIT_MSG@29 PS20, Line 29: 2. Webcam
Please recheck the USB port configuration in devicetree. […]
Ack, as you said, it’ll be fixed in a followup.
https://review.coreboot.org/c/coreboot/+/43760/20/src/mainboard/clevo/kbl-u/... File src/mainboard/clevo/kbl-u/variants/n240bu/overridetree.cb:
PS20:
Please copy the devicetree from N130WU and do you changes there. […]
Done
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43760 )
Change subject: mb/clevo/kbl-u: Add Clevo N240BU as variant ......................................................................
Patch Set 24:
(1 comment)
The wireless device still does not show up, if I am not mistaken.
``` $ lspci -nn 00:00.0 Host bridge [0600]: Intel Corporation Xeon E3-1200 v6/7th Gen Core Processor Host Bridge/DRAM Registers [8086:5904] (rev 02) 00:02.0 VGA compatible controller [0300]: Intel Corporation HD Graphics 620 [8086:5916] (rev 02) 00:04.0 Signal processing controller [1180]: Intel Corporation Xeon E3-1200 v5/E3-1500 v5/6th Gen Core Processor Thermal Subsystem [8086:1903] (rev 02) 00:08.0 System peripheral [0880]: Intel Corporation Xeon E3-1200 v5/v6 / E3-1500 v5 / 6th/7th/8th Gen Core Processor Gaussian Mixture Model [8086:1911] 00:14.0 USB controller [0c03]: Intel Corporation Sunrise Point-LP USB 3.0 xHCI Controller [8086:9d2f] (rev 21) 00:14.2 Signal processing controller [1180]: Intel Corporation Sunrise Point-LP Thermal subsystem [8086:9d31] (rev 21) 00:16.0 Communication controller [0780]: Intel Corporation Sunrise Point-LP CSME HECI #1 [8086:9d3a] (rev 21) 00:17.0 SATA controller [0106]: Intel Corporation Sunrise Point-LP SATA Controller [AHCI mode] [8086:9d03] (rev 21) 00:19.0 Signal processing controller [1180]: Intel Corporation Sunrise Point-LP Serial IO UART Controller #2 [8086:9d66] (rev 21) 00:1c.0 PCI bridge [0604]: Intel Corporation Sunrise Point-LP PCI Express Root Port #3 [8086:9d12] (rev f1) 00:1c.5 PCI bridge [0604]: Intel Corporation Sunrise Point-LP PCI Express Root Port #6 [8086:9d15] (rev f1) 00:1d.0 PCI bridge [0604]: Intel Corporation Sunrise Point-LP PCI Express Root Port #9 [8086:9d18] (rev f1) 00:1f.0 ISA bridge [0601]: Intel Corporation Sunrise Point LPC Controller/eSPI Controller [8086:9d4e] (rev 21) 00:1f.2 Memory controller [0580]: Intel Corporation Sunrise Point-LP PMC [8086:9d21] (rev 21) 00:1f.3 Audio device [0403]: Intel Corporation Sunrise Point-LP HD Audio [8086:9d71] (rev 21) 00:1f.4 SMBus [0c05]: Intel Corporation Sunrise Point-LP SMBus [8086:9d23] (rev 21) 00:1f.5 Non-VGA unclassified device [0000]: Intel Corporation Device [8086:9d24] (rev 21) 02:00.0 Unassigned class [ff00]: Realtek Semiconductor Co., Ltd. RTL8411B PCI Express Card Reader [10ec:5287] (rev 01) 02:00.1 Ethernet controller [0200]: Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 PCI Express Gigabit Ethernet Controller [10ec:8168] (rev 12) 03:00.0 Non-Volatile memory controller [0108]: Samsung Electronics Co Ltd NVMe SSD Controller SM961/PM961 [144d:a804]
```
https://review.coreboot.org/c/coreboot/+/43760/24/src/mainboard/clevo/kbl-u/... File src/mainboard/clevo/kbl-u/variants/n240bu/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/43760/24/src/mainboard/clevo/kbl-u/... PS24, Line 105: register "PcieRpClkReqSupport[1]" = "1" : register "PcieRpClkReqNumber[1]" = "4" : register "PcieRpClkSrcNumber[1]" = "4" : register "PcieRpLtrEnable[1]" = "1" I changed that from 1 to 2.
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43760 )
Change subject: mb/clevo/kbl-u: Add Clevo N240BU as variant ......................................................................
Patch Set 24:
Also, a USB keyboard connected to the right USB-A port works in TianoCore but not in SeaBIOS (master).
Felix Singer has uploaded a new patch set (#25) to the change originally created by Paul Menzel. ( https://review.coreboot.org/c/coreboot/+/43760 )
Change subject: mb/clevo/kbl-u: Add Clevo N240BU as variant ......................................................................
mb/clevo/kbl-u: Add Clevo N240BU as variant
This is the white label device also sold as TUXEDO Book BU1406.
Extracted Video BIOS Option ROM has ID 8086,0406, but the ID of the graphics device differs, but will be mapped to the correct ID.
The system has the subsystem ID below:
Subsystem: CLEVO/KAPOK Computer Xeon E3-1200 v6/7th Gen Core Processor Host Bridge/DRAM Registers
1. SeaBIOS rel-1.14.0-14-g748d619 initializes the display with VBIOS Option ROM. 2. Using GOP for graphics initialization works. 3. Grml 2020.06 on USB flash drive boots. 4. SPI Flash Console works. 5. Debian Sid/unstable with Linux 5.9.6 boots from the NVMe SSD. 6. ACPI S3 resume/suspend works (`freeze`)
Just copy the devicetree from the Clevo N130WU, and adapt it in followups.
Not working:
1. Function keys (EC ACPI missing) 2. Webcam
Change-Id: I57dc2db78c66dd93642f41d10343d1be05fb9f17 Signed-off-by: Paul Menzel pmenzel@molgen.mpg.de --- M src/mainboard/clevo/kbl-u/Kconfig M src/mainboard/clevo/kbl-u/Kconfig.name A src/mainboard/clevo/kbl-u/variants/n240bu/board_info.txt A src/mainboard/clevo/kbl-u/variants/n240bu/data.vbt A src/mainboard/clevo/kbl-u/variants/n240bu/devicetree.cb A src/mainboard/clevo/kbl-u/variants/n240bu/gma-mainboard.ads A src/mainboard/clevo/kbl-u/variants/n240bu/gpio.c A src/mainboard/clevo/kbl-u/variants/n240bu/gpio_early.c A src/mainboard/clevo/kbl-u/variants/n240bu/hda_verb.c 9 files changed, 747 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/43760/25
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43760 )
Change subject: mb/clevo/kbl-u: Add Clevo N240BU as variant ......................................................................
Patch Set 25:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43760/25//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/43760/25//COMMIT_MSG@24 PS25, Line 24: ACPI S3 resume/suspend works (`freeze freeze != ACPI S3 ;; freeze = S0ix
test for S3:
echo deep >/sys/power/mem_sleep echo mem >/sys/power/state
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43760 )
Change subject: mb/clevo/kbl-u: Add Clevo N240BU as variant ......................................................................
Patch Set 25:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43760/25/src/mainboard/clevo/kbl-u/... File src/mainboard/clevo/kbl-u/variants/n240bu/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/43760/25/src/mainboard/clevo/kbl-u/... PS25, Line 92: device pci 1c.0 off end # PCI Express Port 1 No luck in getting the Wifi PCIe device to show up by enabling this port either.
``` diff --git a/src/mainboard/clevo/kbl-u/variants/n240bu/devicetree.cb b/src/mainboard/clevo/kbl-u/variants/n240bu/devicetree.cb index 8a20ca39fc..d6c0f68cd1 100644 --- a/src/mainboard/clevo/kbl-u/variants/n240bu/devicetree.cb +++ b/src/mainboard/clevo/kbl-u/variants/n240bu/devicetree.cb @@ -89,7 +89,12 @@ chip soc/intel/skylake device pci 19.0 on end # UART 2 device pci 19.1 off end # I2C5 device pci 19.2 off end # I2C4 - device pci 1c.0 off end # PCI Express Port 1 + device pci 1c.0 on end # PCI Express Port 1 + register "PcieRpEnable[0]" = "1" + register "PcieRpClkReqSupport[0]" = "1" + register "PcieRpClkReqNumber[0]" = "2" + register "PcieRpClkSrcNumber[0]" = "2" + register "PcieRpLtrEnable[0]" = "1" device pci 1c.1 on # PCI Express Port 2 chip drivers/wifi/generic device pci 00.0 on end # x1 WLAN ```
``` Allocating resources... Reading resources... PCI: 02:00.0 register 10(ffffffff), read-only ignoring it PCI: 02:00.0 register 14(ffffffff), read-only ignoring it PCI: 02:00.0 register 18(ffffffff), read-only ignoring it PCI: 02:00.0 register 1c(ffffffff), read-only ignoring it PCI: 02:00.0 register 20(ffffffff), read-only ignoring it PCI: 02:00.0 register 24(ffffffff), read-only ignoring it PCI: 02:00.0 register 30(ffffffff), read-only ignoring it Done reading resources. ```
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43760 )
Change subject: mb/clevo/kbl-u: Add Clevo N240BU as variant ......................................................................
Patch Set 25:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43760/25/src/mainboard/clevo/kbl-u/... File src/mainboard/clevo/kbl-u/variants/n240bu/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/43760/25/src/mainboard/clevo/kbl-u/... PS25, Line 92: device pci 1c.0 off end # PCI Express Port 1
No luck in getting the Wifi PCIe device to show up by enabling this port either. […]
But the ASMedia device showed up:
01:00.0 USB controller [0c03]: ASMedia Technology Inc. ASM1142 USB 3.1 Host Controller [1b21:1242]
CBMEM console: https://paste.debian.net/1174228/
Hello Felix Singer, build bot (Jenkins), Angel Pons, Michael Niewöhner,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43760
to look at the new patch set (#26).
Change subject: mb/clevo/kbl-u: Add Clevo N240BU as variant ......................................................................
mb/clevo/kbl-u: Add Clevo N240BU as variant
This is the white label device also sold as TUXEDO Book BU1406.
Extracted Video BIOS Option ROM has ID 8086,0406, but the ID of the graphics device differs, but will be mapped to the correct ID.
The system has the subsystem ID below:
Subsystem: CLEVO/KAPOK Computer Xeon E3-1200 v6/7th Gen Core Processor Host Bridge/DRAM Registers
1. SeaBIOS rel-1.14.0-14-g748d619 initializes the display with VBIOS Option ROM. 2. Using GOP for graphics initialization works. 3. Grml 2020.06 on USB flash drive boots. 4. SPI Flash Console works. 5. Debian Sid/unstable with Linux 5.9.6 boots from the NVMe SSD. 6. ACPI S3 resume/suspend works (`freeze`)
Just copy the devicetree from the Clevo N130WU, and adapt it in followups.
Not working:
1. Function keys (EC ACPI missing) 2. Webcam
Change-Id: I57dc2db78c66dd93642f41d10343d1be05fb9f17 Signed-off-by: Paul Menzel pmenzel@molgen.mpg.de --- M src/mainboard/clevo/kbl-u/Kconfig M src/mainboard/clevo/kbl-u/Kconfig.name A src/mainboard/clevo/kbl-u/variants/n240bu/board_info.txt A src/mainboard/clevo/kbl-u/variants/n240bu/data.vbt A src/mainboard/clevo/kbl-u/variants/n240bu/devicetree.cb A src/mainboard/clevo/kbl-u/variants/n240bu/gma-mainboard.ads A src/mainboard/clevo/kbl-u/variants/n240bu/gpio.c A src/mainboard/clevo/kbl-u/variants/n240bu/gpio_early.c A src/mainboard/clevo/kbl-u/variants/n240bu/hda_verb.c 9 files changed, 760 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/43760/26
Hello Felix Singer, build bot (Jenkins), Angel Pons, Michael Niewöhner,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43760
to look at the new patch set (#27).
Change subject: mb/clevo/kbl-u: Add Clevo N240BU as variant ......................................................................
mb/clevo/kbl-u: Add Clevo N240BU as variant
This is the white label device also sold as TUXEDO Book BU1406.
Extracted Video BIOS Option ROM has ID 8086,0406, but the ID of the graphics device differs, but will be mapped to the correct ID.
The system has the subsystem ID below:
Subsystem: CLEVO/KAPOK Computer Xeon E3-1200 v6/7th Gen Core Processor Host Bridge/DRAM Registers
1. SeaBIOS rel-1.14.0-14-g748d619 initializes the display with VBIOS Option ROM. 2. Using GOP for graphics initialization works. 3. Grml 2020.06 on USB flash drive boots. 4. SPI Flash Console works. 5. Debian Sid/unstable with Linux 5.9.6 boots from the NVMe SSD. 6. ACPI S3 resume/suspend works (`freeze`)
Not working:
1. Function keys (EC ACPI missing) 2. Webcam 3. With PcieRpClkReqSupport enabled the Wireless device does not show up.
Change-Id: I57dc2db78c66dd93642f41d10343d1be05fb9f17 Signed-off-by: Paul Menzel pmenzel@molgen.mpg.de --- M src/mainboard/clevo/kbl-u/Kconfig M src/mainboard/clevo/kbl-u/Kconfig.name A src/mainboard/clevo/kbl-u/variants/n240bu/board_info.txt A src/mainboard/clevo/kbl-u/variants/n240bu/data.vbt A src/mainboard/clevo/kbl-u/variants/n240bu/devicetree.cb A src/mainboard/clevo/kbl-u/variants/n240bu/gma-mainboard.ads A src/mainboard/clevo/kbl-u/variants/n240bu/gpio.c A src/mainboard/clevo/kbl-u/variants/n240bu/gpio_early.c A src/mainboard/clevo/kbl-u/variants/n240bu/hda_verb.c 9 files changed, 749 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/43760/27
Felix Singer has uploaded a new patch set (#28) to the change originally created by Paul Menzel. ( https://review.coreboot.org/c/coreboot/+/43760 )
Change subject: mb/clevo/kbl-u: Add Clevo N240BU as variant ......................................................................
mb/clevo/kbl-u: Add Clevo N240BU as variant
This is the white label device also sold as TUXEDO Book BU1406.
Extracted Video BIOS Option ROM has ID 8086,0406, but the ID of the graphics device differs, but will be mapped to the correct ID.
The system has the subsystem ID below:
Subsystem: CLEVO/KAPOK Computer Xeon E3-1200 v6/7th Gen Core Processor Host Bridge/DRAM Registers
1. SeaBIOS rel-1.14.0-14-g748d619 initializes the display with VBIOS Option ROM. 2. Using GOP for graphics initialization works. 3. Grml 2020.06 on USB flash drive boots. 4. SPI Flash Console works. 5. Debian Sid/unstable with Linux 5.9.6 boots from the NVMe SSD. 6. ACPI S3 resume/suspend works (`freeze`)
Not working:
1. Function keys (EC ACPI missing) 2. Webcam 3. With PcieRpClkReqSupport enabled the Wireless device does not show up.
Change-Id: I57dc2db78c66dd93642f41d10343d1be05fb9f17 Signed-off-by: Paul Menzel pmenzel@molgen.mpg.de --- M src/mainboard/clevo/kbl-u/Kconfig M src/mainboard/clevo/kbl-u/Kconfig.name A src/mainboard/clevo/kbl-u/variants/n240bu/board_info.txt A src/mainboard/clevo/kbl-u/variants/n240bu/data.vbt A src/mainboard/clevo/kbl-u/variants/n240bu/devicetree.cb A src/mainboard/clevo/kbl-u/variants/n240bu/gma-mainboard.ads A src/mainboard/clevo/kbl-u/variants/n240bu/gpio.c A src/mainboard/clevo/kbl-u/variants/n240bu/gpio_early.c A src/mainboard/clevo/kbl-u/variants/n240bu/hda_verb.c 9 files changed, 721 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/43760/28
Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43760 )
Change subject: mb/clevo/kbl-u: Add Clevo N240BU as variant ......................................................................
Patch Set 28:
My changes: * Rebased on master * Resolved compiler errors * Moved some options into devicetree * Commented out panel configuration, since I have no idea how the new API works yet * Removed disabled devices (and also GMM) from devicetree, since we have chipset devicetree now and they are not needed
Felix Singer has uploaded a new patch set (#29) to the change originally created by Paul Menzel. ( https://review.coreboot.org/c/coreboot/+/43760 )
Change subject: mb/clevo/kbl-u: Add Clevo N240BU as variant ......................................................................
mb/clevo/kbl-u: Add Clevo N240BU as variant
This is the white label device also sold as TUXEDO Book BU1406.
Extracted Video BIOS Option ROM has ID 8086,0406, but the ID of the graphics device differs, but will be mapped to the correct ID.
The system has the subsystem ID below:
Subsystem: CLEVO/KAPOK Computer Xeon E3-1200 v6/7th Gen Core Processor Host Bridge/DRAM Registers
1. SeaBIOS rel-1.14.0-14-g748d619 initializes the display with VBIOS Option ROM. 2. Using GOP for graphics initialization works. 3. Grml 2020.06 on USB flash drive boots. 4. SPI Flash Console works. 5. Debian Sid/unstable with Linux 5.9.6 boots from the NVMe SSD. 6. ACPI S3 resume/suspend works (`freeze`)
Not working:
1. Function keys (EC ACPI missing) 2. Webcam 3. With PcieRpClkReqSupport enabled the Wireless device does not show up.
Change-Id: I57dc2db78c66dd93642f41d10343d1be05fb9f17 Signed-off-by: Paul Menzel pmenzel@molgen.mpg.de --- M src/mainboard/clevo/kbl-u/Kconfig M src/mainboard/clevo/kbl-u/Kconfig.name A src/mainboard/clevo/kbl-u/variants/n240bu/board_info.txt A src/mainboard/clevo/kbl-u/variants/n240bu/data.vbt A src/mainboard/clevo/kbl-u/variants/n240bu/devicetree.cb A src/mainboard/clevo/kbl-u/variants/n240bu/gma-mainboard.ads A src/mainboard/clevo/kbl-u/variants/n240bu/gpio.c A src/mainboard/clevo/kbl-u/variants/n240bu/gpio_early.c A src/mainboard/clevo/kbl-u/variants/n240bu/hda_verb.c 9 files changed, 725 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/43760/29
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43760 )
Change subject: mb/clevo/kbl-u: Add Clevo N240BU as variant ......................................................................
Patch Set 29:
(5 comments)
Patch Set 28:
My changes: ...
- Commented out panel configuration, since I have no idea how the new API works yet
didn't change much; it's a struct now, but the names are mostly the same. check cml-u
https://review.coreboot.org/c/coreboot/+/43760/29//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/43760/29//COMMIT_MSG@12 PS29, Line 12: but will be mapped to the correct ID "... in soc code." I guess
https://review.coreboot.org/c/coreboot/+/43760/29//COMMIT_MSG@20 PS29, Line 20: Using GOP what about libgfxinit?
https://review.coreboot.org/c/coreboot/+/43760/29//COMMIT_MSG@30 PS29, Line 30: 3. With PcieRpClkReqSupport enabled the Wireless device does not show up. uhm, didn't we investigate and solve that? I don't remember
https://review.coreboot.org/c/coreboot/+/43760/29/src/mainboard/clevo/kbl-u/... File src/mainboard/clevo/kbl-u/variants/n240bu/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/43760/29/src/mainboard/clevo/kbl-u/... PS29, Line 37: "GMA_STATIC_DISPLAYS(0)" use the new GMA_DEFAULT_PANEL(0)
https://review.coreboot.org/c/coreboot/+/43760/29/src/mainboard/clevo/kbl-u/... PS29, Line 38: u_pp_up_delay_ms" = "200" # T3 : # register "gpu_pp_down_delay_ms" = " 0" # T10 : # register "gpu_pp_cycle_delay_ms" = "500" # T12 : # register "gpu_pp_backlight_on_delay_ms" = " 50" # T7 : # register "gpu_pp_backlight_off_delay_ms" = " 0" # T9 : # register "gpu_pch_backlight_pwm_hz" = "200" convert this to the new format; see cml-u
Attention is currently required from: Felix Singer. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43760 )
Change subject: mb/clevo/kbl-u: Add Clevo N240BU as variant ......................................................................
Patch Set 30:
(1 comment)
Patchset:
PS30: Unfortunately, the power jack is broken again (it was repaired already once), so I am unable to test this.
Martin L Roth has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/43760?usp=email )
Change subject: mb/clevo/kbl-u: Add Clevo N240BU as variant ......................................................................
Abandoned
This patch has not been touched in over 12 months. Anyone who wants to take over work on this patch, please feel free to restore it and do any work needed to get it merged. If you create a new patch based on this work, please credit the original author.
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Angel Pons (Code Review) -
Felix Singer (Code Review)
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Martin L Roth (Code Review)
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Michael Niewöhner (Code Review)
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Paul Menzel (Code Review)