Paul Menzel has uploaded this change for review.
mb/clevo/kbl-u: Add Clevo N240BU as variant
This is the board used in the Tuxedo BU1406. The ID of the graphics device differs.
Change-Id: I57dc2db78c66dd93642f41d10343d1be05fb9f17
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
---
M src/mainboard/clevo/kbl-u/Kconfig
M src/mainboard/clevo/kbl-u/Kconfig.name
M src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb
A src/mainboard/clevo/kbl-u/variants/n240bu/data.vbt
A src/mainboard/clevo/kbl-u/variants/n240bu/devicetree.cb
5 files changed, 267 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/43760/1
diff --git a/src/mainboard/clevo/kbl-u/Kconfig b/src/mainboard/clevo/kbl-u/Kconfig
index a54d487..adb807a 100644
--- a/src/mainboard/clevo/kbl-u/Kconfig
+++ b/src/mainboard/clevo/kbl-u/Kconfig
@@ -1,4 +1,4 @@
-if BOARD_CLEVO_N130WU || BOARD_CLEVO_N131WU
+if BOARD_CLEVO_N130WU || BOARD_CLEVO_N131WU || BOARD_CLEVO_N240BU
config BOARD_SPECIFIC_OPTIONS
def_bool y
@@ -14,6 +14,7 @@
select MAINBOARD_HAS_LPC_TPM
select MAINBOARD_HAS_TPM2
select NO_UART_ON_SUPERIO
+ select SOC_INTEL_COMMON_BLOCK
select SOC_INTEL_COMMON_BLOCK_HDA_VERB
select SOC_INTEL_KABYLAKE
select SPD_READ_BY_WORD
@@ -38,11 +39,13 @@
config VARIANT_DIR
string
default "n13xwu" if BOARD_CLEVO_N130WU || BOARD_CLEVO_N131WU
+ default "n240bu" if BOARD_CLEVO_N240BU
config MAINBOARD_PART_NUMBER
string
default "N130WU" if BOARD_CLEVO_N130WU
default "N131WU" if BOARD_CLEVO_N131WU
+ default "N240BU" if BOARD_CLEVO_N240BU
config DEVICETREE
string
@@ -51,6 +54,7 @@
config CBFS_SIZE
hex
default 0x600000 if !VBOOT
+ default 0x500000 if BOARD_CLEVO_N240BU
config FMDFILE
string
@@ -62,7 +66,7 @@
config MAX_CPUS
int
- default 8 if BOARD_CLEVO_N130WU || BOARD_CLEVO_N131WU
+ default 8 if BOARD_CLEVO_N130WU || BOARD_CLEVO_N131WU || BOARD_CLEVO_N240BU
config DIMM_MAX
int
@@ -78,24 +82,22 @@
config SUBSYSTEM_DEVICE_ID
hex
- default 0x1313 if BOARD_CLEVO_N130WU || BOARD_CLEVO_N131WU
+ default 0x1313 if BOARD_CLEVO_N130WU || BOARD_CLEVO_N131WU || BOARD_CLEVO_N240BU
config VGA_BIOS_FILE
string
+ default "pci8086,5916.rom" if BOARD_CLEVO_N240BU
default "pci8086,5917.rom" if BOARD_CLEVO_N130WU || BOARD_CLEVO_N131WU
config VGA_BIOS_ID
string
+ default "8086,5916" if BOARD_CLEVO_N240BU
default "8086,5917" if BOARD_CLEVO_N130WU || BOARD_CLEVO_N131WU
config PXE_ROM_ID
string
default "10ec,8168"
-config FSP_M_XIP
- bool
- default y
-
config UART_FOR_CONSOLE
int
default 2
diff --git a/src/mainboard/clevo/kbl-u/Kconfig.name b/src/mainboard/clevo/kbl-u/Kconfig.name
index f252f0b..98e0217 100644
--- a/src/mainboard/clevo/kbl-u/Kconfig.name
+++ b/src/mainboard/clevo/kbl-u/Kconfig.name
@@ -3,3 +3,6 @@
config BOARD_CLEVO_N131WU
bool "N131WU"
+
+config BOARD_CLEVO_N240BU
+ bool "N240BU"
diff --git a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb
index 91252c1..ef0f938 100644
--- a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb
+++ b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb
@@ -213,11 +213,11 @@
device domain 0 on
device pci 00.0 on end # Host Bridge
device pci 02.0 on end # Integrated Graphics Device
+ device pci 08.0 off end # Gaussian Mixture Model
device pci 14.0 on end # USB xHCI
- device pci 14.1 off end # USB xDCI (OTG)
device pci 14.2 on end # Thermal Subsystem
device pci 16.0 off end # Management Engine Interface 1
- device pci 16.1 off end # Management Engine Interface 2
+ device pci 16.1 off end # Management Engine Inte2rface 2
device pci 16.2 off end # Management Engine IDE-R
device pci 16.3 off end # Management Engine KT Redirection
device pci 16.4 off end # Management Engine Interface 3
diff --git a/src/mainboard/clevo/kbl-u/variants/n240bu/data.vbt b/src/mainboard/clevo/kbl-u/variants/n240bu/data.vbt
new file mode 100644
index 0000000..d85368b
--- /dev/null
+++ b/src/mainboard/clevo/kbl-u/variants/n240bu/data.vbt
Binary files differ
diff --git a/src/mainboard/clevo/kbl-u/variants/n240bu/devicetree.cb b/src/mainboard/clevo/kbl-u/variants/n240bu/devicetree.cb
new file mode 100644
index 0000000..699211f
--- /dev/null
+++ b/src/mainboard/clevo/kbl-u/variants/n240bu/devicetree.cb
@@ -0,0 +1,253 @@
+chip soc/intel/skylake
+ # Disable deep Sx states
+ register "deep_s3_enable_ac" = "0"
+ register "deep_s3_enable_dc" = "0"
+ register "deep_s5_enable_ac" = "0"
+ register "deep_s5_enable_dc" = "0"
+ register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"
+
+ register "eist_enable" = "1"
+
+ # GPE configuration
+ # Note that GPE events called out in ASL code rely on this
+ # route. i.e. If this route changes then the affected GPE
+ # offset bits also need to be changed.
+ register "gpe0_dw0" = "GPP_E"
+ register "gpe0_dw1" = "GPP_A"
+ register "gpe0_dw2" = "GPP_C"
+
+ register "gen1_dec" = "0x000c0681"
+ register "gen2_dec" = "0x000c1641"
+ register "gen3_dec" = "0x000c0081"
+ register "gen4_dec" = "0x00040069"
+
+ # Enable "Intel Speed Shift Technology"
+ register "speed_shift_enable" = "1"
+
+ # Disable DPTF
+ register "dptf_enable" = "0"
+
+ # FSP Configuration
+ register "ProbelessTrace" = "0"
+ register "EnableLan" = "0"
+ register "EnableSata" = "1"
+ register "SataSalpSupport" = "0"
+ register "SataMode" = "0"
+ register "SataPortsEnable[0]" = "1"
+ register "SataPortsEnable[1]" = "0"
+ register "SataPortsEnable[2]" = "1"
+ register "SataPortsDevSlp[0]" = "0"
+ register "SataPortsDevSlp[2]" = "0"
+ register "SataSpeedLimit" = "2"
+ register "EnableAzalia" = "1"
+ register "DspEnable" = "0"
+ register "IoBufferOwnership" = "0"
+ register "EnableTraceHub" = "0"
+ register "SsicPortEnable" = "0"
+ register "SmbusEnable" = "1"
+ register "Cio2Enable" = "0"
+ register "ScsEmmcEnabled" = "0"
+ register "ScsEmmcHs400Enabled" = "0"
+ register "ScsSdCardEnabled" = "0"
+ register "PttSwitch" = "0"
+ register "SkipExtGfxScan" = "1"
+ register "Device4Enable" = "1"
+ register "HeciEnabled" = "1"
+ register "SaGv" = "3"
+ register "PmConfigSlpS3MinAssert" = "2" # 50ms
+ register "PmConfigSlpS4MinAssert" = "1" # 1s
+ register "PmConfigSlpSusMinAssert" = "3" # 500ms
+ register "PmConfigSlpAMinAssert" = "3" # 2s
+ register "PmTimerDisabled" = "0"
+
+ register "serirq_mode" = "SERIRQ_CONTINUOUS"
+
+ register "pirqa_routing" = "PCH_IRQ11"
+ register "pirqb_routing" = "PCH_IRQ10"
+ register "pirqc_routing" = "PCH_IRQ11"
+ register "pirqd_routing" = "PCH_IRQ11"
+ register "pirqe_routing" = "PCH_IRQ11"
+ register "pirqf_routing" = "PCH_IRQ11"
+ register "pirqg_routing" = "PCH_IRQ11"
+ register "pirqh_routing" = "PCH_IRQ11"
+
+ # Root port #1 x4 (TBT)
+ register "PcieRpEnable[0]" = "1"
+ register "PcieRpClkReqSupport[0]" = "1"
+ register "PcieRpClkReqNumber[0]" = "4"
+ register "PcieRpClkSrcNumber[0]" = "4"
+ register "PcieRpAdvancedErrorReporting[0]" = "1"
+ register "PcieRpLtrEnable[0]" = "1"
+ register "PcieRpHotPlug[0]" = "1"
+
+ # Root port #5 x1 (LAN)
+ register "PcieRpEnable[4]" = "1"
+ register "PcieRpClkReqSupport[4]" = "1"
+ register "PcieRpClkReqNumber[4]" = "3"
+ register "PcieRpClkSrcNumber[4]" = "3"
+ register "PcieRpAdvancedErrorReporting[4]" = "1"
+ register "PcieRpLtrEnable[4]" = "1"
+
+ # Root port #6 x1 (WLAN)
+ register "PcieRpEnable[5]" = "1"
+ register "PcieRpClkReqSupport[5]" = "1"
+ register "PcieRpClkReqNumber[5]" = "2"
+ register "PcieRpClkSrcNumber[5]" = "2"
+ register "PcieRpAdvancedErrorReporting[5]" = "1"
+ register "PcieRpLtrEnable[5]" = "1"
+
+ # Root port #9 x4 (NVMe)
+ register "PcieRpEnable[8]" = "1"
+ register "PcieRpClkReqSupport[8]" = "1"
+ register "PcieRpClkReqNumber[8]" = "5"
+ register "PcieRpClkSrcNumber[8]" = "5"
+ register "PcieRpAdvancedErrorReporting[8]" = "1"
+ register "PcieRpLtrEnable[8]" = "1"
+
+ # Configure USB2 ports
+ register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A port right
+ register "usb2_ports[1]" = "USB2_PORT_FLEX(OC_SKIP)" # 3G / LTE
+ register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C port right
+ register "usb2_ports[3]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera
+ register "usb2_ports[4]" = "USB2_PORT_FLEX(OC_SKIP)" # Bluetooth
+ register "usb2_ports[5]" = "USB2_PORT_EMPTY" # NC
+ register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Type-A port left
+ register "usb2_ports[7]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C port right
+ register "usb2_ports[8]" = "USB2_PORT_EMPTY" # NC
+ register "usb2_ports[9]" = "USB2_PORT_EMPTY" # NC
+
+ # Configure USB3 ports
+ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port right
+ register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # 4G
+ register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type C port right
+ register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port left
+
+ # Send an extra VR mailbox command for the PS4 exit issue
+ register "SendVrMbxCmd" = "2"
+
+ # PL1 override 25W
+ # PL2 override 44W
+ register "power_limits_config" = "{
+ .tdp_pl1_override = 25,
+ .tdp_pl2_override = 44,
+ }"
+
+ # VR Settings Configuration for 4 Domains
+ #+----------------+-----------+-----------+-------------+----------+
+ #| Domain/Setting | SA | IA | GT Unsliced | GT |
+ #+----------------+-----------+-----------+-------------+----------+
+ #| Psi1Threshold | 20A | 20A | 20A | 20A |
+ #| Psi2Threshold | 4A | 5A | 5A | 5A |
+ #| Psi3Threshold | 1A | 1A | 1A | 1A |
+ #| Psi3Enable | 1 | 1 | 1 | 1 |
+ #| Psi4Enable | 1 | 1 | 1 | 1 |
+ #| ImonSlope | 0 | 0 | 0 | 0 |
+ #| ImonOffset | 0 | 0 | 0 | 0 |
+ #| IccMax | 5A | 64A | 31A | 31A |
+ #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
+ #+----------------+-----------+-----------+-------------+----------+
+ register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(4),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 0,
+ .psi4enable = 0,
+ .imon_slope = 0x0,
+ .imon_offset = 0x0,
+ .icc_max = VR_CFG_AMP(5),
+ .voltage_limit = 1520,
+ .ac_loadline = 1030,
+ .dc_loadline = 1030,
+ }"
+
+ register "domain_vr_config[VR_IA_CORE]" = "{
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(5),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 0,
+ .psi4enable = 0,
+ .imon_slope = 0x0,
+ .imon_offset = 0x0,
+ .icc_max = VR_CFG_AMP(64),
+ .voltage_limit = 1520,
+ .ac_loadline = 240,
+ .dc_loadline = 240,
+ }"
+
+ register "domain_vr_config[VR_GT_UNSLICED]" = "{
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(5),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 0,
+ .psi4enable = 0,
+ .imon_slope = 0x0,
+ .imon_offset = 0x0,
+ .icc_max = VR_CFG_AMP(31),
+ .voltage_limit = 1520,
+ .ac_loadline = 310,
+ .dc_loadline = 310,
+ }"
+
+ register "domain_vr_config[VR_GT_SLICED]" = "{
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(5),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 0,
+ .psi4enable = 0,
+ .imon_slope = 0x0,
+ .imon_offset = 0x0,
+ .icc_max = VR_CFG_AMP(31),
+ .voltage_limit = 1520,
+ .ac_loadline = 310,
+ .dc_loadline = 310,
+ }"
+
+ # Lock Down
+ register "common_soc_config" = "{
+ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
+ }"
+
+ device cpu_cluster 0 on
+ device lapic 0 on end
+ end
+ device domain 0 on
+ device pci 00.0 on end # Host Bridge
+ device pci 02.0 on end # Integrated Graphics Device
+ device pci 14.0 on end # USB xHCI
+ device pci 14.1 off end # USB xDCI (OTG)
+ device pci 14.2 on end # Thermal Subsystem
+ device pci 16.0 off end # Management Engine Interface 1
+ device pci 16.1 off end # Management Engine Interface 2
+ device pci 16.2 off end # Management Engine IDE-R
+ device pci 16.3 off end # Management Engine KT Redirection
+ device pci 16.4 off end # Management Engine Interface 3
+ device pci 17.0 on end # SATA
+ device pci 1c.0 on end # PCI Express Port 1
+ device pci 1c.1 off end # PCI Express Port 2
+ device pci 1c.2 off end # PCI Express Port 3
+ device pci 1c.3 off end # PCI Express Port 4
+ device pci 1c.4 on end # PCI Express Port 5
+ device pci 1c.5 on end # PCI Express Port 6
+ device pci 1c.6 off end # PCI Express Port 7
+ device pci 1c.7 off end # PCI Express Port 8
+ device pci 1d.0 on end # PCI Express Port 9
+ device pci 1d.1 off end # PCI Express Port 10
+ device pci 1d.2 off end # PCI Express Port 11
+ device pci 1d.3 off end # PCI Express Port 12
+ device pci 1f.0 on
+ chip drivers/pc80/tpm
+ device pnp 0c31.0 on end
+ end
+ end # LPC Interface
+ device pci 1f.1 off end # P2SB
+ device pci 1f.2 on end # Power Management Controller
+ device pci 1f.3 on end # Intel HDA
+ device pci 1f.4 on end # SMBus
+ device pci 1f.5 off end # PCH SPI
+ device pci 1f.6 off end # GbE
+ end
+end
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