Change in ...coreboot[master]: soc/intel/skylake: remove PrimaryDisplay check

[Maxim Polyakov (Code Review)]

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32615

Change subject: soc/intel/skylake: remove PrimaryDisplay check
......................................................................

soc/intel/skylake: remove PrimaryDisplay check

Checking the PrimaryDisplay parameter (added by patch with Change
Id Ie3f9362676105e41c69139a094dbb9e8b865689f) isn`t required. The
display connected to PEG works  even if IGD is primary for output
image and at the same time this device is disabled

Tested on Asrock H110M-DVS with NVIDIA GTX 1060 GPU
Payload: tianocore edk2-stable201811-216-g51be9d0

Change-Id: I5615597881a151bb004676d914fbf40874ac1f68
Signed-off-by: Maxim Polyakov 
---
M src/soc/intel/skylake/romstage/romstage_fsp20.c
1 file changed, 1 insertion(+), 5 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/32615/1

diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c
index c166e3a..2f75479 100644
--- a/src/soc/intel/skylake/romstage/romstage_fsp20.c
+++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c
@@ -304,10 +304,6 @@
    	 */
    	m_cfg->InternalGfx = 0;
    	m_cfg->IgdDvmt50PreAlloc = 0;
-		if (config->PrimaryDisplay == Display_iGFX)
-			m_cfg->PrimaryDisplay = Display_Auto;
-		else
-			m_cfg->PrimaryDisplay = config->PrimaryDisplay;
    } else {
    	m_cfg->InternalGfx = 1;
    	/*
@@ -319,8 +315,8 @@
    	 * a high resolution panel
    	 */
    	m_cfg->IgdDvmt50PreAlloc = 2;
-		m_cfg->PrimaryDisplay = config->PrimaryDisplay;
    }
+	m_cfg->PrimaryDisplay = config->PrimaryDisplay;
 }

void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)

[Nico Huber (Code Review)]

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32615 )

Change subject: soc/intel/skylake: remove PrimaryDisplay check
......................................................................

Patch Set 1: Code-Review+2

Thanks, for the update.

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32615 )

Change subject: soc/intel/skylake: remove PrimaryDisplay check
......................................................................

Patch Set 2: Code-Review+2

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32615 )

Change subject: soc/intel/skylake: remove PrimaryDisplay check
......................................................................

soc/intel/skylake: remove PrimaryDisplay check

Checking the PrimaryDisplay parameter (added by patch with Change
Id Ie3f9362676105e41c69139a094dbb9e8b865689f) isn`t required. The
display connected to PEG works  even if IGD is primary for output
image and at the same time this device is disabled

Tested on Asrock H110M-DVS with NVIDIA GTX 1060 GPU
Payload: tianocore edk2-stable201811-216-g51be9d0

Change-Id: I5615597881a151bb004676d914fbf40874ac1f68
Signed-off-by: Maxim Polyakov 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32615
Reviewed-by: Furquan Shaikh 
Reviewed-by: Nico Huber 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/skylake/romstage/romstage_fsp20.c
1 file changed, 1 insertion(+), 5 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Nico Huber: Looks good to me, approved
  Furquan Shaikh: Looks good to me, approved

diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c
index c166e3a..2f75479 100644
--- a/src/soc/intel/skylake/romstage/romstage_fsp20.c
+++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c
@@ -304,10 +304,6 @@
    	 */
    	m_cfg->InternalGfx = 0;
    	m_cfg->IgdDvmt50PreAlloc = 0;
-		if (config->PrimaryDisplay == Display_iGFX)
-			m_cfg->PrimaryDisplay = Display_Auto;
-		else
-			m_cfg->PrimaryDisplay = config->PrimaryDisplay;
    } else {
    	m_cfg->InternalGfx = 1;
    	/*
@@ -319,8 +315,8 @@
    	 * a high resolution panel
    	 */
    	m_cfg->IgdDvmt50PreAlloc = 2;
-		m_cfg->PrimaryDisplay = config->PrimaryDisplay;
    }
+	m_cfg->PrimaryDisplay = config->PrimaryDisplay;
 }

void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)