the following patch was just integrated into master: commit f4b20af9d716ff57d78d5d576e2990903bd70842 Author: Furquan Shaikh furquan@chromium.org Date: Mon Feb 20 13:33:32 2017 -0800
drivers/intel/{fsp1_1,fsp2_0}: Provide separate function for fsp load
Add a function to allow FSP component loading separately from silicon initialization. This enables SoCs that might not have stage cache available during silicon initialization to load/save components from/to stage cache before it is relocated or destroyed.
BUG=chrome-os-partner:63114 BRANCH=None TEST=Compiles successfully.
Change-Id: Iae77e20568418c29df9f69bd54aa571e153740c9 Signed-off-by: Furquan Shaikh furquan@chromium.org Reviewed-on: https://review.coreboot.org/18413 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik subrata.banik@intel.com Reviewed-by: Aaron Durbin adurbin@chromium.org
See https://review.coreboot.org/18413 for details.
-gerrit