Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40731 )
Change subject: mb/ocp/tiogapass: rework GPIOs configuration using macros ......................................................................
mb/ocp/tiogapass: rework GPIOs configuration using macros
This format of PCH GPIOs configuration, unlike the raw DW0 and DW1 registers values from the inteltool dump, is more understandable and makes the code much cleaner. The gpio.h file with PAD_CFG macros was automatically generated using the util/intelp2m [1] utility:
./intelp2m -p lbg -file tiogapass/vendorbios/inteltool_gpio.log
According to the documentation [2], the Host Software Pad Ownership register only affects the pads that are configured as input. The intelp2m utility takes this into account when converting macros and ignores bits from this register for the corresponding pads. However, the PAD_CFG_GPO_GPIO_DRIVER() macros are still used, since these macros were added to the project for a long time ago and some motherboards use them in the configuration. The issue related to these macros should be resolved in a separate patch.
[1] https://review.coreboot.org/c/coreboot/+/35643 [2] Intel Document Number: 549921
Change-Id: I21e98721e58b00be9196927837daa2b5d2560822 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/mainboard/ocp/tiogapass/gpio.h 1 file changed, 241 insertions(+), 241 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/40731/1
diff --git a/src/mainboard/ocp/tiogapass/gpio.h b/src/mainboard/ocp/tiogapass/gpio.h index 823f797..77ae5ff 100644 --- a/src/mainboard/ocp/tiogapass/gpio.h +++ b/src/mainboard/ocp/tiogapass/gpio.h @@ -11,534 +11,534 @@ /* ------- GPIO Community 0 ------- */ /* ------- GPIO Group GPP_A ------- */ /* GPP_A0 - GPIO */ - _PAD_CFG_STRUCT(GPP_A0, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_A0, NONE, DEEP, OFF, DRIVER), /* GPP_A1 - LAD0 */ - _PAD_CFG_STRUCT(GPP_A1, 0x44000402, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_A1, NONE, DEEP, NF1, NO_DISABLE, OFF), /* GPP_A2 - LAD1 */ - _PAD_CFG_STRUCT(GPP_A2, 0x44000402, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_A2, NONE, DEEP, NF1, NO_DISABLE, OFF), /* GPP_A3 - LAD2 */ - _PAD_CFG_STRUCT(GPP_A3, 0x44000402, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_A3, NONE, DEEP, NF1, NO_DISABLE, OFF), /* GPP_A4 - LAD3 */ - _PAD_CFG_STRUCT(GPP_A4, 0x44000402, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_A4, NONE, DEEP, NF1, NO_DISABLE, OFF), /* GPP_A5 - LFRAME# */ - _PAD_CFG_STRUCT(GPP_A5, 0x44000600, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_A5, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_A6 - SERIRQ */ - _PAD_CFG_STRUCT(GPP_A6, 0x44000502, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_A6, NONE, DEEP, NF1, TX_DISABLE, OFF), /* GPP_A7 - PIRQA# */ - _PAD_CFG_STRUCT(GPP_A7, 0x44000502, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_A7, NONE, DEEP, NF1, TX_DISABLE, OFF), /* GPP_A8 - CLKRUN# */ - _PAD_CFG_STRUCT(GPP_A8, 0x44000500, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_A8, NONE, DEEP, NF1, TX_DISABLE, OFF), /* GPP_A9 - CLKOUT_LPC0 */ - _PAD_CFG_STRUCT(GPP_A9, 0x44000600, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_A9, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_A10 - GPIO */ - _PAD_CFG_STRUCT(GPP_A10, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_A10, NONE, DEEP, OFF, DRIVER), /* GPP_A11 - GPIO */ - _PAD_CFG_STRUCT(GPP_A11, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_A11, NONE, DEEP, OFF, DRIVER), /* GPP_A12 - GPIO */ - _PAD_CFG_STRUCT(GPP_A12, 0x84000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_A12, NONE, PLTRST, OFF, DRIVER), /* GPP_A13 - GPIO */ - _PAD_CFG_STRUCT(GPP_A13, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_A13, NONE, DEEP, OFF, DRIVER), /* GPP_A14 - GPIO */ - _PAD_CFG_STRUCT(GPP_A14, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_A14, NONE, DEEP, OFF, DRIVER), /* GPP_A15 - GPIO */ - _PAD_CFG_STRUCT(GPP_A15, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_A15, NONE, DEEP, OFF, DRIVER), /* GPP_A16 - GPIO */ - _PAD_CFG_STRUCT(GPP_A16, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_A16, NONE, DEEP, OFF, DRIVER), /* GPP_A17 - GPIO */ - _PAD_CFG_STRUCT(GPP_A17, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_A17, NONE, DEEP, OFF, DRIVER), /* GPP_A18 - GPIO */ - _PAD_CFG_STRUCT(GPP_A18, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_A18, NONE, DEEP, OFF, DRIVER), /* GPP_A19 - RESERVED */ /* GPP_A20 - GPIO */ - _PAD_CFG_STRUCT(GPP_A20, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_A20, NONE, DEEP, OFF, DRIVER), /* GPP_A21 - GPIO */ - _PAD_CFG_STRUCT(GPP_A21, 0x44000201, 0x00000010), + PAD_CFG_GPO_GPIO_DRIVER(GPP_A21, 1, DEEP, NONE), /* GPP_A22 - GPIO */ - _PAD_CFG_STRUCT(GPP_A22, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_A22, NONE, DEEP, OFF, DRIVER), /* GPP_A23 - GPIO */ - _PAD_CFG_STRUCT(GPP_A23, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_A23, NONE, DEEP, OFF, DRIVER),
/* ------- GPIO Group GPP_B ------- */ /* GPP_B0 - CORE_VID0 */ - _PAD_CFG_STRUCT(GPP_B0, 0x44000600, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_B0, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_B1 - CORE_VID1 */ - _PAD_CFG_STRUCT(GPP_B1, 0x44000600, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_B1, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_B2 - GPIO */ - _PAD_CFG_STRUCT(GPP_B2, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_B2, NONE, DEEP, OFF, DRIVER), /* GPP_B3 - GPIO */ - _PAD_CFG_STRUCT(GPP_B3, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_B3, NONE, DEEP, OFF, DRIVER), /* GPP_B4 - GPIO */ - _PAD_CFG_STRUCT(GPP_B4, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_B4, NONE, DEEP, OFF, DRIVER), /* GPP_B5 - GPIO */ - _PAD_CFG_STRUCT(GPP_B5, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_B5, NONE, DEEP, OFF, DRIVER), /* GPP_B6 - GPIO */ - _PAD_CFG_STRUCT(GPP_B6, 0x84000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_B6, NONE, PLTRST, OFF, DRIVER), /* GPP_B7 - GPIO */ - _PAD_CFG_STRUCT(GPP_B7, 0x84000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_B7, NONE, PLTRST, OFF, DRIVER), /* GPP_B8 - GPIO */ - _PAD_CFG_STRUCT(GPP_B8, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_B8, NONE, DEEP, OFF, DRIVER), /* GPP_B9 - GPIO */ - _PAD_CFG_STRUCT(GPP_B9, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_B9, NONE, DEEP, OFF, DRIVER), /* GPP_B10 - GPIO */ - _PAD_CFG_STRUCT(GPP_B10, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_B10, NONE, DEEP, OFF, DRIVER), /* GPP_B11 - GPIO */ - _PAD_CFG_STRUCT(GPP_B11, 0x44000201, 0x00000010), + PAD_CFG_GPO_GPIO_DRIVER(GPP_B11, 1, DEEP, NONE), /* GPP_B12 - GLB_RST_WARN_N# */ - _PAD_CFG_STRUCT(GPP_B12, 0x44000600, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_B12, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_B13 - PLTRST# */ - _PAD_CFG_STRUCT(GPP_B13, 0x44000600, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_B13, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_B14 - SPKR */ - _PAD_CFG_STRUCT(GPP_B14, 0x44000600, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_B14, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_B15 - GPIO */ - _PAD_CFG_STRUCT(GPP_B15, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_B15, NONE, DEEP, OFF, DRIVER), /* GPP_B16 - GPIO */ - _PAD_CFG_STRUCT(GPP_B16, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_B16, NONE, DEEP, OFF, DRIVER), /* GPP_B17 - GPIO */ - _PAD_CFG_STRUCT(GPP_B17, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_B17, NONE, DEEP, OFF, DRIVER), /* GPP_B18 - GPIO */ - _PAD_CFG_STRUCT(GPP_B18, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_B18, NONE, DEEP, OFF, DRIVER), /* GPP_B19 - GPIO */ - _PAD_CFG_STRUCT(GPP_B19, 0x44000201, 0x00000010), + PAD_CFG_GPO_GPIO_DRIVER(GPP_B19, 1, DEEP, NONE), /* GPP_B20 - GPIO */ - _PAD_CFG_STRUCT(GPP_B20, 0x44000200, 0x00000010), + PAD_CFG_GPO_GPIO_DRIVER(GPP_B20, 0, DEEP, NONE), /* GPP_B21 - GPIO */ - _PAD_CFG_STRUCT(GPP_B21, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_B21, NONE, DEEP, OFF, DRIVER), /* GPP_B22 - GPIO */ - _PAD_CFG_STRUCT(GPP_B22, 0x44000200, 0x00000010), + PAD_CFG_GPO_GPIO_DRIVER(GPP_B22, 0, DEEP, NONE), /* GPP_B23 - PCHHOT# */ - _PAD_CFG_STRUCT(GPP_B23, 0x00000a00, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_B23, NONE, RSMRST, NF2, RX_DISABLE, LEVEL),
/* ------- GPIO Group GPP_F ------- */ /* GPP_F0 - GPIO */ - _PAD_CFG_STRUCT(GPP_F0, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_F0, NONE, DEEP, OFF, DRIVER), /* GPP_F1 - GPIO */ - _PAD_CFG_STRUCT(GPP_F1, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_F1, NONE, DEEP, OFF, DRIVER), /* GPP_F2 - GPIO */ - _PAD_CFG_STRUCT(GPP_F2, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_F2, NONE, DEEP, OFF, DRIVER), /* GPP_F3 - GPIO */ - _PAD_CFG_STRUCT(GPP_F3, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_F3, NONE, DEEP, OFF, DRIVER), /* GPP_F4 - GPIO */ - _PAD_CFG_STRUCT(GPP_F4, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_F4, NONE, DEEP, OFF, DRIVER), /* GPP_F5 - GPIO */ - _PAD_CFG_STRUCT(GPP_F5, 0x44000101, 0x00000010), + _PAD_CFG_STRUCT(GPP_F5, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), /* GPP_F6 - GPIO */ - _PAD_CFG_STRUCT(GPP_F6, 0x84000200, 0x00000010), + PAD_CFG_GPO_GPIO_DRIVER(GPP_F6, 0, PLTRST, NONE), /* GPP_F7 - GPIO */ - _PAD_CFG_STRUCT(GPP_F7, 0x84000200, 0x00000010), + PAD_CFG_GPO_GPIO_DRIVER(GPP_F7, 0, PLTRST, NONE), /* GPP_F8 - GPIO */ - _PAD_CFG_STRUCT(GPP_F8, 0x84000200, 0x00000010), + PAD_CFG_GPO_GPIO_DRIVER(GPP_F8, 0, PLTRST, NONE), /* GPP_F9 - GPIO */ - _PAD_CFG_STRUCT(GPP_F9, 0x84000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_F9, NONE, PLTRST, OFF, DRIVER), /* GPP_F10 - SATA_SCLOCK */ - _PAD_CFG_STRUCT(GPP_F10, 0x44000600, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_F10, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_F11 - SATA_SLOAD */ - _PAD_CFG_STRUCT(GPP_F11, 0x44000600, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_F11, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_F12 - GPIO */ - _PAD_CFG_STRUCT(GPP_F12, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_F12, NONE, DEEP, OFF, DRIVER), /* GPP_F13 - SATA_SDATAOUT2 */ - _PAD_CFG_STRUCT(GPP_F13, 0x44000600, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_F13, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_F14 - SSATA_LED# */ - _PAD_CFG_STRUCT(GPP_F14, 0x44000e00, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_F14, NONE, DEEP, NF3, RX_DISABLE, OFF), /* GPP_F15 - GPIO */ - _PAD_CFG_STRUCT(GPP_F15, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_F15, NONE, DEEP, OFF, DRIVER), /* GPP_F16 - GPIO */ - _PAD_CFG_STRUCT(GPP_F16, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_F16, NONE, DEEP, OFF, DRIVER), /* GPP_F17 - GPIO */ - _PAD_CFG_STRUCT(GPP_F17, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_F17, NONE, DEEP, OFF, DRIVER), /* GPP_F18 - GPIO */ - _PAD_CFG_STRUCT(GPP_F18, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_F18, NONE, DEEP, OFF, DRIVER), /* GPP_F19 - LAN_SMBCLK */ - _PAD_CFG_STRUCT(GPP_F19, 0x44000502, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_F19, NONE, DEEP, NF1, TX_DISABLE, OFF), /* GPP_F20 - LAN_SMBDATA */ - _PAD_CFG_STRUCT(GPP_F20, 0x44000502, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_F20, NONE, DEEP, NF1, TX_DISABLE, OFF), /* GPP_F21 - LAN_SMBALRT# */ - _PAD_CFG_STRUCT(GPP_F21, 0x44000602, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_F21, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_F22 - SSATA_SCLOCK */ - _PAD_CFG_STRUCT(GPP_F22, 0x44000e00, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_F22, NONE, DEEP, NF3, RX_DISABLE, OFF), /* GPP_F23 - SSATA_SLOAD */ - _PAD_CFG_STRUCT(GPP_F23, 0x44000e00, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_F23, NONE, DEEP, NF3, RX_DISABLE, OFF),
/* ------- GPIO Community 1 ------- */ /* ------- GPIO Group GPP_C ------- */ /* GPP_C0 - RESERVED */ /* GPP_C1 - RESERVED */ /* GPP_C2 - SMBALERT# */ - _PAD_CFG_STRUCT(GPP_C2, 0x44000502, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_C2, NONE, DEEP, NF1, TX_DISABLE, OFF), /* GPP_C3 - RESERVED */ /* GPP_C4 - RESERVED */ /* GPP_C5 - GPIO */ - _PAD_CFG_STRUCT(GPP_C5, 0x44000200, 0x00000000), + PAD_CFG_GPO(GPP_C5, 0, DEEP), /* GPP_C6 - RESERVED */ /* GPP_C7 - RESERVED */ /* GPP_C8 - GPIO */ - _PAD_CFG_STRUCT(GPP_C8, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_C8, NONE, DEEP, OFF, DRIVER), /* GPP_C9 - GPIO */ - _PAD_CFG_STRUCT(GPP_C9, 0x44000201, 0x00000010), + PAD_CFG_GPO_GPIO_DRIVER(GPP_C9, 1, DEEP, NONE), /* GPP_C10 - GPIO */ - _PAD_CFG_STRUCT(GPP_C10, 0x86000103, 0x00000000), + _PAD_CFG_STRUCT(GPP_C10, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_CFG0_TRIG_EDGE_BOTH | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), /* GPP_C11 - GPIO */ - _PAD_CFG_STRUCT(GPP_C11, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_C11, NONE, DEEP, OFF, DRIVER), /* GPP_C12 - GPIO */ - _PAD_CFG_STRUCT(GPP_C12, 0x44000103, 0x00000010), + _PAD_CFG_STRUCT(GPP_C12, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), /* GPP_C13 - GPIO */ - _PAD_CFG_STRUCT(GPP_C13, 0x44000103, 0x00000010), + _PAD_CFG_STRUCT(GPP_C13, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), /* GPP_C14 - GPIO */ - _PAD_CFG_STRUCT(GPP_C14, 0x80080102, 0x00000000), + PAD_CFG_GPI_SCI(GPP_C14, NONE, PLTRST, LEVEL, NONE), /* GPP_C15 - GPIO */ - _PAD_CFG_STRUCT(GPP_C15, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_C15, NONE, DEEP, OFF, DRIVER), /* GPP_C16 - GPIO */ - _PAD_CFG_STRUCT(GPP_C16, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_C16, NONE, DEEP, OFF, DRIVER), /* GPP_C17 - GPIO */ - _PAD_CFG_STRUCT(GPP_C17, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_C17, NONE, DEEP, OFF, DRIVER), /* GPP_C18 - GPIO */ - _PAD_CFG_STRUCT(GPP_C18, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_C18, NONE, DEEP, OFF, DRIVER), /* GPP_C19 - GPIO */ - _PAD_CFG_STRUCT(GPP_C19, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_C19, NONE, DEEP, OFF, DRIVER), /* GPP_C20 - RESERVED */ /* GPP_C21 - GPIO */ - _PAD_CFG_STRUCT(GPP_C21, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_C21, NONE, DEEP, OFF, DRIVER), /* GPP_C22 - GPIO */ - _PAD_CFG_STRUCT(GPP_C22, 0x80040102, 0x00000000), + PAD_CFG_GPI_SMI(GPP_C22, NONE, PLTRST, LEVEL, NONE), /* GPP_C23 - GPIO */ - _PAD_CFG_STRUCT(GPP_C23, 0x40840102, 0x00000000), + PAD_CFG_GPI_SMI(GPP_C23, NONE, DEEP, LEVEL, INVERT),
/* ------- GPIO Group GPP_D ------- */ /* GPP_D0 - GPIO */ - _PAD_CFG_STRUCT(GPP_D0, 0x80840102, 0x00000000), + PAD_CFG_GPI_SMI(GPP_D0, NONE, PLTRST, LEVEL, INVERT), /* GPP_D1 - GPIO */ - _PAD_CFG_STRUCT(GPP_D1, 0x44000200, 0x00000010), + PAD_CFG_GPO_GPIO_DRIVER(GPP_D1, 0, DEEP, NONE), /* GPP_D2 - GPIO */ - _PAD_CFG_STRUCT(GPP_D2, 0x84000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_D2, NONE, PLTRST, OFF, DRIVER), /* GPP_D3 - GPIO */ - _PAD_CFG_STRUCT(GPP_D3, 0x84000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_D3, NONE, PLTRST, OFF, DRIVER), /* GPP_D4 - GPIO */ - _PAD_CFG_STRUCT(GPP_D4, 0x44000201, 0x00000010), + PAD_CFG_GPO_GPIO_DRIVER(GPP_D4, 1, DEEP, NONE), /* GPP_D5 - GPIO */ - _PAD_CFG_STRUCT(GPP_D5, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_D5, NONE, DEEP, OFF, DRIVER), /* GPP_D6 - GPIO */ - _PAD_CFG_STRUCT(GPP_D6, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_D6, NONE, DEEP, OFF, DRIVER), /* GPP_D7 - GPIO */ - _PAD_CFG_STRUCT(GPP_D7, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_D7, NONE, DEEP, OFF, DRIVER), /* GPP_D8 - GPIO */ - _PAD_CFG_STRUCT(GPP_D8, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_D8, NONE, DEEP, OFF, DRIVER), /* GPP_D9 - GPIO */ - _PAD_CFG_STRUCT(GPP_D9, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_D9, NONE, DEEP, OFF, DRIVER), /* GPP_D10 - GPIO */ - _PAD_CFG_STRUCT(GPP_D10, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_D10, NONE, DEEP, OFF, DRIVER), /* GPP_D11 - GPIO */ - _PAD_CFG_STRUCT(GPP_D11, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_D11, NONE, DEEP, OFF, DRIVER), /* GPP_D12 - GPIO */ - _PAD_CFG_STRUCT(GPP_D12, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_D12, NONE, DEEP, OFF, DRIVER), /* GPP_D13 - GPIO */ - _PAD_CFG_STRUCT(GPP_D13, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_D13, NONE, DEEP, OFF, DRIVER), /* GPP_D14 - GPIO */ - _PAD_CFG_STRUCT(GPP_D14, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_D14, NONE, DEEP, OFF, DRIVER), /* GPP_D15 - SSATA_SDATAOUT0 */ - _PAD_CFG_STRUCT(GPP_D15, 0x44000e00, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_D15, NONE, DEEP, NF3, RX_DISABLE, OFF), /* GPP_D16 - GPIO */ - _PAD_CFG_STRUCT(GPP_D16, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_D16, NONE, DEEP, OFF, DRIVER), /* GPP_D17 - GPIO */ - _PAD_CFG_STRUCT(GPP_D17, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_D17, NONE, DEEP, OFF, DRIVER), /* GPP_D18 - GPIO */ - _PAD_CFG_STRUCT(GPP_D18, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_D18, NONE, DEEP, OFF, DRIVER), /* GPP_D19 - GPIO */ - _PAD_CFG_STRUCT(GPP_D19, 0x44000201, 0x00000010), + PAD_CFG_GPO_GPIO_DRIVER(GPP_D19, 1, DEEP, NONE), /* GPP_D20 - GPIO */ - _PAD_CFG_STRUCT(GPP_D20, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_D20, NONE, DEEP, OFF, DRIVER), /* GPP_D21 - GPIO */ - _PAD_CFG_STRUCT(GPP_D21, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_D21, NONE, DEEP, OFF, DRIVER), /* GPP_D22 - GPIO */ - _PAD_CFG_STRUCT(GPP_D22, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_D22, NONE, DEEP, OFF, DRIVER), /* GPP_D23 - GPIO */ - _PAD_CFG_STRUCT(GPP_D23, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_D23, NONE, DEEP, OFF, DRIVER),
/* ------- GPIO Group GPP_E ------- */ /* GPP_E0 - GPIO */ - _PAD_CFG_STRUCT(GPP_E0, 0x40040102, 0x00000010), + PAD_CFG_GPI_SMI(GPP_E0, NONE, DEEP, LEVEL, NONE), /* GPP_E1 - GPIO */ - _PAD_CFG_STRUCT(GPP_E1, 0x40040102, 0x00000010), + PAD_CFG_GPI_SMI(GPP_E1, NONE, DEEP, LEVEL, NONE), /* GPP_E2 - GPIO */ - _PAD_CFG_STRUCT(GPP_E2, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_E2, NONE, DEEP, OFF, DRIVER), /* GPP_E3 - CPU_GP0 */ - _PAD_CFG_STRUCT(GPP_E3, 0x44000502, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_E3, NONE, DEEP, NF1, TX_DISABLE, OFF), /* GPP_E4 - GPIO */ - _PAD_CFG_STRUCT(GPP_E4, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_E4, NONE, DEEP, OFF, DRIVER), /* GPP_E5 - GPIO */ - _PAD_CFG_STRUCT(GPP_E5, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_E5, NONE, DEEP, OFF, DRIVER), /* GPP_E6 - GPIO */ - _PAD_CFG_STRUCT(GPP_E6, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_E6, NONE, DEEP, OFF, DRIVER), /* GPP_E7 - GPIO */ - _PAD_CFG_STRUCT(GPP_E7, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_E7, NONE, DEEP, OFF, DRIVER), /* GPP_E8 - SATA_LED# */ - _PAD_CFG_STRUCT(GPP_E8, 0x44000600, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_E8, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_E9 - USB_OC0# */ - _PAD_CFG_STRUCT(GPP_E9, 0x44000502, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_E9, NONE, DEEP, NF1, TX_DISABLE, OFF), /* GPP_E10 - GPIO */ - _PAD_CFG_STRUCT(GPP_E10, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_E10, NONE, DEEP, OFF, DRIVER), /* GPP_E11 - GPIO */ - _PAD_CFG_STRUCT(GPP_E11, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_E11, NONE, DEEP, OFF, DRIVER), /* GPP_E12 - GPIO */ - _PAD_CFG_STRUCT(GPP_E12, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_E12, NONE, DEEP, OFF, DRIVER),
/* ------- GPIO Community 2 ------- */ /* -------- GPIO Group GPD -------- */ /* GPD0 - RESERVED */ /* GPD1 - GPIO */ - _PAD_CFG_STRUCT(GPD1, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPD1, NONE, RSMRST, OFF, ACPI), /* GPD2 - GPIO */ - _PAD_CFG_STRUCT(GPD2, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPD2, NONE, RSMRST, OFF, ACPI), /* GPD3 - PWRBTN# */ - _PAD_CFG_STRUCT(GPD3, 0x04000502, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPD3, NONE, RSMRST, NF1, TX_DISABLE, OFF), /* GPD4 - SLP_S3# */ - _PAD_CFG_STRUCT(GPD4, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPD4, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPD5 - SLP_S4# */ - _PAD_CFG_STRUCT(GPD5, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPD5, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPD6 - GPIO */ - _PAD_CFG_STRUCT(GPD6, 0x04000100, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPD6, NONE, RSMRST, OFF, ACPI), /* GPD7 - GPIO */ - _PAD_CFG_STRUCT(GPD7, 0x04000103, 0x00000000), + _PAD_CFG_STRUCT(GPD7, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), /* GPD8 - GPIO */ - _PAD_CFG_STRUCT(GPD8, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPD8, NONE, RSMRST, OFF, ACPI), /* GPD9 - GPIO */ - _PAD_CFG_STRUCT(GPD9, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPD9, NONE, RSMRST, OFF, ACPI), /* GPD10 - GPIO */ - _PAD_CFG_STRUCT(GPD10, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPD10, NONE, RSMRST, OFF, ACPI), /* GPD11 - GBEPHY */ - _PAD_CFG_STRUCT(GPD11, 0x04000500, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPD11, NONE, RSMRST, NF1, TX_DISABLE, OFF),
/* ------- GPIO Community 3 ------- */ /* ------- GPIO Group GPP_I ------- */ /* GPP_I0 - LAN_TDO */ - _PAD_CFG_STRUCT(GPP_I0, 0x44000900, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_I0, NONE, DEEP, NF2, TX_DISABLE, OFF), /* GPP_I1 - LAN_TCK */ - _PAD_CFG_STRUCT(GPP_I1, 0x44000a02, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_I1, NONE, DEEP, NF2, RX_DISABLE, OFF), /* GPP_I2 - LAN_TMS */ - _PAD_CFG_STRUCT(GPP_I2, 0x44000a02, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_I2, NONE, DEEP, NF2, RX_DISABLE, OFF), /* GPP_I3 - LAN_TDI */ - _PAD_CFG_STRUCT(GPP_I3, 0x44000a02, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_I3, NONE, DEEP, NF2, RX_DISABLE, OFF), /* GPP_I4 - GPIO */ - _PAD_CFG_STRUCT(GPP_I4, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_I4, NONE, DEEP, OFF, DRIVER), /* GPP_I5 - GPIO */ - _PAD_CFG_STRUCT(GPP_I5, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_I5, NONE, DEEP, OFF, DRIVER), /* GPP_I6 - GPIO */ - _PAD_CFG_STRUCT(GPP_I6, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_I6, NONE, DEEP, OFF, DRIVER), /* GPP_I7 - LAN_TRST_IN */ - _PAD_CFG_STRUCT(GPP_I7, 0x44000902, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_I7, NONE, DEEP, NF2, TX_DISABLE, OFF), /* GPP_I8 - GPIO */ - _PAD_CFG_STRUCT(GPP_I8, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_I8, NONE, DEEP, OFF, DRIVER), /* GPP_I9 - GPIO */ - _PAD_CFG_STRUCT(GPP_I9, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_I9, NONE, DEEP, OFF, DRIVER), /* GPP_I10 - GPIO */ - _PAD_CFG_STRUCT(GPP_I10, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_I10, NONE, DEEP, OFF, DRIVER),
/* ------- GPIO Community 4 ------- */ /* ------- GPIO Group GPP_J ------- */ /* GPP_J0 - LAN_LED_P0_0 */ - _PAD_CFG_STRUCT(GPP_J0, 0x44000600, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_J0, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_J1 - LAN_LED_P0_1 */ - _PAD_CFG_STRUCT(GPP_J1, 0x44000600, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_J1, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_J2 - LAN_LED_P1_0 */ - _PAD_CFG_STRUCT(GPP_J2, 0x44000600, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_J2, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_J3 - LAN_LED_P1_1 */ - _PAD_CFG_STRUCT(GPP_J3, 0x44000600, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_J3, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_J4 - LAN_LED_P2_0 */ - _PAD_CFG_STRUCT(GPP_J4, 0x44000600, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_J4, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_J5 - LAN_LED_P2_1 */ - _PAD_CFG_STRUCT(GPP_J5, 0x44000600, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_J5, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_J6 - LAN_LED_P3_0 */ - _PAD_CFG_STRUCT(GPP_J6, 0x44000600, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_J6, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_J7 - LAN_LED_P3_1 */ - _PAD_CFG_STRUCT(GPP_J7, 0x44000600, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_J7, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_J8 - LAN_I2C_SCL_MDC_P0 */ - _PAD_CFG_STRUCT(GPP_J8, 0x44000602, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_J8, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_J9 - LAN_I2C_SDA_MDIO_P0 */ - _PAD_CFG_STRUCT(GPP_J9, 0x44000402, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_J9, NONE, DEEP, NF1, NO_DISABLE, OFF), /* GPP_J10 - LAN_I2C_SCL_MDC_P1 */ - _PAD_CFG_STRUCT(GPP_J10, 0x44000602, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_J10, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_J11 - LAN_I2C_SDA_MDIO_P1 */ - _PAD_CFG_STRUCT(GPP_J11, 0x44000402, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_J11, NONE, DEEP, NF1, NO_DISABLE, OFF), /* GPP_J12 - LAN_I2C_SCL_MDC_P2 */ - _PAD_CFG_STRUCT(GPP_J12, 0x44000602, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_J12, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_J13 - LAN_I2C_SDA_MDIO_P2 */ - _PAD_CFG_STRUCT(GPP_J13, 0x44000402, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_J13, NONE, DEEP, NF1, NO_DISABLE, OFF), /* GPP_J14 - LAN_I2C_SCL_MDC_P3 */ - _PAD_CFG_STRUCT(GPP_J14, 0x44000602, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_J14, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_J15 - LAN_I2C_SDA_MDIO_P3 */ - _PAD_CFG_STRUCT(GPP_J15, 0x44000402, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_J15, NONE, DEEP, NF1, NO_DISABLE, OFF), /* GPP_J16 - LAN_SDP_P0_0 */ - _PAD_CFG_STRUCT(GPP_J16, 0x44000502, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_J16, NONE, DEEP, NF1, TX_DISABLE, OFF), /* GPP_J17 - GPIO */ - _PAD_CFG_STRUCT(GPP_J17, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_J17, NONE, DEEP, OFF, DRIVER), /* GPP_J18 - LAN_SDP_P1_0 */ - _PAD_CFG_STRUCT(GPP_J18, 0x44000502, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_J18, NONE, DEEP, NF1, TX_DISABLE, OFF), /* GPP_J19 - GPIO */ - _PAD_CFG_STRUCT(GPP_J19, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_J19, NONE, DEEP, OFF, DRIVER), /* GPP_J20 - LAN_SDP_P2_0 */ - _PAD_CFG_STRUCT(GPP_J20, 0x44000502, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_J20, NONE, DEEP, NF1, TX_DISABLE, OFF), /* GPP_J21 - GPIO */ - _PAD_CFG_STRUCT(GPP_J21, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_J21, NONE, DEEP, OFF, DRIVER), /* GPP_J22 - LAN_SDP_P3_0 */ - _PAD_CFG_STRUCT(GPP_J22, 0x44000502, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_J22, NONE, DEEP, NF1, TX_DISABLE, OFF), /* GPP_J23 - GPIO */ - _PAD_CFG_STRUCT(GPP_J23, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_J23, NONE, DEEP, OFF, DRIVER),
/* ------- GPIO Group GPP_K ------- */ /* GPP_K0 - GPIO */ - _PAD_CFG_STRUCT(GPP_K0, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_K0, NONE, DEEP, OFF, DRIVER), /* GPP_K1 - GPIO */ - _PAD_CFG_STRUCT(GPP_K1, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_K1, NONE, DEEP, OFF, DRIVER), /* GPP_K2 - GPIO */ - _PAD_CFG_STRUCT(GPP_K2, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_K2, NONE, DEEP, OFF, DRIVER), /* GPP_K3 - GPIO */ - _PAD_CFG_STRUCT(GPP_K3, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_K3, NONE, DEEP, OFF, DRIVER), /* GPP_K4 - GPIO */ - _PAD_CFG_STRUCT(GPP_K4, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_K4, NONE, DEEP, OFF, DRIVER), /* GPP_K5 - GPIO */ - _PAD_CFG_STRUCT(GPP_K5, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_K5, NONE, DEEP, OFF, DRIVER), /* GPP_K6 - GPIO */ - _PAD_CFG_STRUCT(GPP_K6, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_K6, NONE, DEEP, OFF, DRIVER), /* GPP_K7 - RESERVED */ - _PAD_CFG_STRUCT(GPP_K7, 0x44000600, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_K7, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_K8 - LAN_NCSI_ARB_IN */ - _PAD_CFG_STRUCT(GPP_K8, 0x44000502, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_K8, NONE, DEEP, NF1, TX_DISABLE, OFF), /* GPP_K9 - LAN_NCSI_ARB_OUT */ - _PAD_CFG_STRUCT(GPP_K9, 0x44000602, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_K9, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_K10 - PE_RST# */ - _PAD_CFG_STRUCT(GPP_K10, 0x44000502, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_K10, NONE, DEEP, NF1, TX_DISABLE, OFF),
/* ------- GPIO Community 5 ------- */ /* ------- GPIO Group GPP_G ------- */ /* GPP_G0 - GPIO */ - _PAD_CFG_STRUCT(GPP_G0, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_G0, NONE, DEEP, OFF, DRIVER), /* GPP_G1 - GPIO */ - _PAD_CFG_STRUCT(GPP_G1, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_G1, NONE, DEEP, OFF, DRIVER), /* GPP_G2 - GPIO */ - _PAD_CFG_STRUCT(GPP_G2, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_G2, NONE, DEEP, OFF, DRIVER), /* GPP_G3 - GPIO */ - _PAD_CFG_STRUCT(GPP_G3, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_G3, NONE, DEEP, OFF, DRIVER), /* GPP_G4 - GPIO */ - _PAD_CFG_STRUCT(GPP_G4, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_G4, NONE, DEEP, OFF, DRIVER), /* GPP_G5 - GPIO */ - _PAD_CFG_STRUCT(GPP_G5, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_G5, NONE, DEEP, OFF, DRIVER), /* GPP_G6 - GPIO */ - _PAD_CFG_STRUCT(GPP_G6, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_G6, NONE, DEEP, OFF, DRIVER), /* GPP_G7 - GPIO */ - _PAD_CFG_STRUCT(GPP_G7, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_G7, NONE, DEEP, OFF, DRIVER), /* GPP_G8 - GPIO */ - _PAD_CFG_STRUCT(GPP_G8, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_G8, NONE, DEEP, OFF, DRIVER), /* GPP_G9 - GPIO */ - _PAD_CFG_STRUCT(GPP_G9, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_G9, NONE, DEEP, OFF, DRIVER), /* GPP_G10 - GPIO */ - _PAD_CFG_STRUCT(GPP_G10, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_G10, NONE, DEEP, OFF, DRIVER), /* GPP_G11 - GPIO */ - _PAD_CFG_STRUCT(GPP_G11, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_G11, NONE, DEEP, OFF, DRIVER), /* GPP_G12 - GPIO */ - _PAD_CFG_STRUCT(GPP_G12, 0x44000103, 0x00000010), + _PAD_CFG_STRUCT(GPP_G12, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), /* GPP_G13 - GPIO */ - _PAD_CFG_STRUCT(GPP_G13, 0x44000103, 0x00000010), + _PAD_CFG_STRUCT(GPP_G13, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), /* GPP_G14 - GPIO */ - _PAD_CFG_STRUCT(GPP_G14, 0x44000101, 0x00000010), + _PAD_CFG_STRUCT(GPP_G14, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), /* GPP_G15 - GPIO */ - _PAD_CFG_STRUCT(GPP_G15, 0x44000101, 0x00000010), + _PAD_CFG_STRUCT(GPP_G15, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), /* GPP_G16 - GPIO */ - _PAD_CFG_STRUCT(GPP_G16, 0x44000101, 0x00000010), + _PAD_CFG_STRUCT(GPP_G16, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), /* GPP_G17 - ADR_COMPLETE */ - _PAD_CFG_STRUCT(GPP_G17, 0x44000600, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_G17, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_G18 - NMI# */ - _PAD_CFG_STRUCT(GPP_G18, 0x44000600, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_G18, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_G19 - SMI# */ - _PAD_CFG_STRUCT(GPP_G19, 0x44000600, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_G19, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_G20 - RESERVED */ /* GPP_G21 - GPIO */ - _PAD_CFG_STRUCT(GPP_G21, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_G21, NONE, DEEP, OFF, DRIVER), /* GPP_G22 - GPIO */ - _PAD_CFG_STRUCT(GPP_G22, 0x44000201, 0x00000010), + PAD_CFG_GPO_GPIO_DRIVER(GPP_G22, 1, DEEP, NONE), /* GPP_G23 - GPIO */ - _PAD_CFG_STRUCT(GPP_G23, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_G23, NONE, DEEP, OFF, DRIVER),
/* ------- GPIO Group GPP_H ------- */ /* GPP_H0 - GPIO */ - _PAD_CFG_STRUCT(GPP_H0, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_H0, NONE, DEEP, OFF, DRIVER), /* GPP_H1 - GPIO */ - _PAD_CFG_STRUCT(GPP_H1, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_H1, NONE, DEEP, OFF, DRIVER), /* GPP_H2 - GPIO */ - _PAD_CFG_STRUCT(GPP_H2, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_H2, NONE, DEEP, OFF, DRIVER), /* GPP_H3 - GPIO */ - _PAD_CFG_STRUCT(GPP_H3, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_H3, NONE, DEEP, OFF, DRIVER), /* GPP_H4 - GPIO */ - _PAD_CFG_STRUCT(GPP_H4, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_H4, NONE, DEEP, OFF, DRIVER), /* GPP_H5 - RESERVED */ /* GPP_H6 - GPIO */ - _PAD_CFG_STRUCT(GPP_H6, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_H6, NONE, DEEP, OFF, DRIVER), /* GPP_H7 - GPIO */ - _PAD_CFG_STRUCT(GPP_H7, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_H7, NONE, DEEP, OFF, DRIVER), /* GPP_H8 - GPIO */ - _PAD_CFG_STRUCT(GPP_H8, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_H8, NONE, DEEP, OFF, DRIVER), /* GPP_H9 - GPIO */ - _PAD_CFG_STRUCT(GPP_H9, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_H9, NONE, DEEP, OFF, DRIVER), /* GPP_H10 - RESERVED */ /* GPP_H11 - RESERVED */ /* GPP_H12 - GPIO */ - _PAD_CFG_STRUCT(GPP_H12, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_H12, NONE, DEEP, OFF, DRIVER), /* GPP_H13 - RESERVED */ /* GPP_H14 - RESERVED */ /* GPP_H15 - GPIO */ - _PAD_CFG_STRUCT(GPP_H15, 0x84000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_H15, NONE, PLTRST, OFF, DRIVER), /* GPP_H16 - RESERVED */ /* GPP_H17 - RESERVED */ /* GPP_H18 - GPIO */ - _PAD_CFG_STRUCT(GPP_H18, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_H18, NONE, DEEP, OFF, DRIVER), /* GPP_H19 - GPIO */ - _PAD_CFG_STRUCT(GPP_H19, 0x84000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_H19, NONE, PLTRST, OFF, DRIVER), /* GPP_H20 - GPIO */ - _PAD_CFG_STRUCT(GPP_H20, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_H20, NONE, DEEP, OFF, DRIVER), /* GPP_H21 - GPIO */ - _PAD_CFG_STRUCT(GPP_H21, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_H21, NONE, DEEP, OFF, DRIVER), /* GPP_H22 - GPIO */ - _PAD_CFG_STRUCT(GPP_H22, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_H22, NONE, DEEP, OFF, DRIVER), /* GPP_H23 - GPIO */ - _PAD_CFG_STRUCT(GPP_H23, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_H23, NONE, DEEP, OFF, DRIVER),
/* ------- GPIO Group GPP_L ------- */ /* GPP_L0 - RESERVED */ /* GPP_L1 - CSME_INTR_OUT */ - _PAD_CFG_STRUCT(GPP_L1, 0x44000700, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_L1, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* GPP_L2 - GPIO */ - _PAD_CFG_STRUCT(GPP_L2, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_L2, NONE, DEEP, OFF, DRIVER), /* GPP_L3 - GPIO */ - _PAD_CFG_STRUCT(GPP_L3, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_L3, NONE, DEEP, OFF, DRIVER), /* GPP_L4 - GPIO */ - _PAD_CFG_STRUCT(GPP_L4, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_L4, NONE, DEEP, OFF, DRIVER), /* GPP_L5 - GPIO */ - _PAD_CFG_STRUCT(GPP_L5, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_L5, NONE, DEEP, OFF, DRIVER), /* GPP_L6 - GPIO */ - _PAD_CFG_STRUCT(GPP_L6, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_L6, NONE, DEEP, OFF, DRIVER), /* GPP_L7 - GPIO */ - _PAD_CFG_STRUCT(GPP_L7, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_L7, NONE, DEEP, OFF, DRIVER), /* GPP_L8 - GPIO */ - _PAD_CFG_STRUCT(GPP_L8, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_L8, NONE, DEEP, OFF, DRIVER), /* GPP_L9 - GPIO */ - _PAD_CFG_STRUCT(GPP_L9, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_L9, NONE, DEEP, OFF, DRIVER), /* GPP_L10 - GPIO */ - _PAD_CFG_STRUCT(GPP_L10, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_L10, NONE, DEEP, OFF, DRIVER), /* GPP_L11 - GPIO */ - _PAD_CFG_STRUCT(GPP_L11, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_L11, NONE, DEEP, OFF, DRIVER), /* GPP_L12 - GPIO */ - _PAD_CFG_STRUCT(GPP_L12, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_L12, NONE, DEEP, OFF, DRIVER), /* GPP_L13 - GPIO */ - _PAD_CFG_STRUCT(GPP_L13, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_L13, NONE, DEEP, OFF, DRIVER), /* GPP_L14 - GPIO */ - _PAD_CFG_STRUCT(GPP_L14, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_L14, NONE, DEEP, OFF, DRIVER), /* GPP_L15 - GPIO */ - _PAD_CFG_STRUCT(GPP_L15, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_L15, NONE, DEEP, OFF, DRIVER), /* GPP_L16 - GPIO */ - _PAD_CFG_STRUCT(GPP_L16, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_L16, NONE, DEEP, OFF, DRIVER), /* GPP_L17 - GPIO */ - _PAD_CFG_STRUCT(GPP_L17, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_L17, NONE, DEEP, OFF, DRIVER), /* GPP_L18 - GPIO */ - _PAD_CFG_STRUCT(GPP_L18, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_L18, NONE, DEEP, OFF, DRIVER), /* GPP_L19 - GPIO */ - _PAD_CFG_STRUCT(GPP_L19, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_L19, NONE, DEEP, OFF, DRIVER), };
#endif /* CFG_PCH_GPIO_H */
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40731 )
Change subject: mb/ocp/tiogapass: rework GPIOs configuration using macros ......................................................................
Patch Set 1:
(10 comments)
https://review.coreboot.org/c/coreboot/+/40731/1/src/mainboard/ocp/tiogapass... File src/mainboard/ocp/tiogapass/gpio.h:
https://review.coreboot.org/c/coreboot/+/40731/1/src/mainboard/ocp/tiogapass... PS1, Line 123: _PAD_CFG_STRUCT(GPP_F5, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40731/1/src/mainboard/ocp/tiogapass... PS1, Line 178: _PAD_CFG_STRUCT(GPP_C10, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_CFG0_TRIG_EDGE_BOTH | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40731/1/src/mainboard/ocp/tiogapass... PS1, Line 182: _PAD_CFG_STRUCT(GPP_C12, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40731/1/src/mainboard/ocp/tiogapass... PS1, Line 184: _PAD_CFG_STRUCT(GPP_C13, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40731/1/src/mainboard/ocp/tiogapass... PS1, Line 299: _PAD_CFG_STRUCT(GPD7, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40731/1/src/mainboard/ocp/tiogapass... PS1, Line 436: _PAD_CFG_STRUCT(GPP_G12, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40731/1/src/mainboard/ocp/tiogapass... PS1, Line 438: _PAD_CFG_STRUCT(GPP_G13, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40731/1/src/mainboard/ocp/tiogapass... PS1, Line 440: _PAD_CFG_STRUCT(GPP_G14, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40731/1/src/mainboard/ocp/tiogapass... PS1, Line 442: _PAD_CFG_STRUCT(GPP_G15, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40731/1/src/mainboard/ocp/tiogapass... PS1, Line 444: _PAD_CFG_STRUCT(GPP_G16, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), line over 96 characters
Maxim Polyakov has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/40731 )
Change subject: mb/ocp/tiogapass: rework GPIOs configuration using macros ......................................................................
mb/ocp/tiogapass: rework GPIOs configuration using macros
This format of PCH GPIOs configuration, unlike the raw DW0 and DW1 registers values from the inteltool dump, is more understandable and makes the code much cleaner. The gpio.h file with PAD_CFG macros was automatically generated using the util/intelp2m [1] utility:
./intelp2m -p lbg -file tiogapass/vendorbios/inteltool_gpio.log
According to the documentation [2], the Host Software Pad Ownership register only affects the pads that are configured as input. The intelp2m utility takes this into account when converting macros and ignores bits from this register for the corresponding pads. However, the PAD_CFG_GPO_GPIO_DRIVER() macros are still used, since these macros were added to the project for a long time ago and some motherboards use them in the configuration. The issue related to these macros should be resolved in a separate patch.
[1] https://review.coreboot.org/c/coreboot/+/35643 [2] Intel Document Number: 549921
Change-Id: I21e98721e58b00be9196927837daa2b5d2560822 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/mainboard/ocp/tiogapass/gpio.h 1 file changed, 241 insertions(+), 241 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/40731/2
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40731 )
Change subject: mb/ocp/tiogapass: rework GPIOs configuration using macros ......................................................................
Patch Set 2:
(10 comments)
https://review.coreboot.org/c/coreboot/+/40731/2/src/mainboard/ocp/tiogapass... File src/mainboard/ocp/tiogapass/gpio.h:
https://review.coreboot.org/c/coreboot/+/40731/2/src/mainboard/ocp/tiogapass... PS2, Line 123: _PAD_CFG_STRUCT(GPP_F5, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40731/2/src/mainboard/ocp/tiogapass... PS2, Line 178: _PAD_CFG_STRUCT(GPP_C10, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_CFG0_TRIG_EDGE_BOTH | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40731/2/src/mainboard/ocp/tiogapass... PS2, Line 182: _PAD_CFG_STRUCT(GPP_C12, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40731/2/src/mainboard/ocp/tiogapass... PS2, Line 184: _PAD_CFG_STRUCT(GPP_C13, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40731/2/src/mainboard/ocp/tiogapass... PS2, Line 299: _PAD_CFG_STRUCT(GPD7, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40731/2/src/mainboard/ocp/tiogapass... PS2, Line 436: _PAD_CFG_STRUCT(GPP_G12, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40731/2/src/mainboard/ocp/tiogapass... PS2, Line 438: _PAD_CFG_STRUCT(GPP_G13, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40731/2/src/mainboard/ocp/tiogapass... PS2, Line 440: _PAD_CFG_STRUCT(GPP_G14, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40731/2/src/mainboard/ocp/tiogapass... PS2, Line 442: _PAD_CFG_STRUCT(GPP_G15, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40731/2/src/mainboard/ocp/tiogapass... PS2, Line 444: _PAD_CFG_STRUCT(GPP_G16, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), line over 96 characters
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40731 )
Change subject: mb/ocp/tiogapass: rework GPIOs configuration using macros ......................................................................
Patch Set 3:
(10 comments)
https://review.coreboot.org/c/coreboot/+/40731/3/src/mainboard/ocp/tiogapass... File src/mainboard/ocp/tiogapass/gpio.h:
https://review.coreboot.org/c/coreboot/+/40731/3/src/mainboard/ocp/tiogapass... PS3, Line 123: _PAD_CFG_STRUCT(GPP_F5, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40731/3/src/mainboard/ocp/tiogapass... PS3, Line 178: _PAD_CFG_STRUCT(GPP_C10, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_CFG0_TRIG_EDGE_BOTH | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40731/3/src/mainboard/ocp/tiogapass... PS3, Line 182: _PAD_CFG_STRUCT(GPP_C12, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40731/3/src/mainboard/ocp/tiogapass... PS3, Line 184: _PAD_CFG_STRUCT(GPP_C13, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40731/3/src/mainboard/ocp/tiogapass... PS3, Line 299: _PAD_CFG_STRUCT(GPD7, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40731/3/src/mainboard/ocp/tiogapass... PS3, Line 436: _PAD_CFG_STRUCT(GPP_G12, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40731/3/src/mainboard/ocp/tiogapass... PS3, Line 438: _PAD_CFG_STRUCT(GPP_G13, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40731/3/src/mainboard/ocp/tiogapass... PS3, Line 440: _PAD_CFG_STRUCT(GPP_G14, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40731/3/src/mainboard/ocp/tiogapass... PS3, Line 442: _PAD_CFG_STRUCT(GPP_G15, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40731/3/src/mainboard/ocp/tiogapass... PS3, Line 444: _PAD_CFG_STRUCT(GPP_G16, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), line over 96 characters
Andrey Petrov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40731 )
Change subject: mb/ocp/tiogapass: rework GPIOs configuration using macros ......................................................................
Patch Set 3: Code-Review+1
Hello build bot (Jenkins), Andrey Petrov,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40731
to look at the new patch set (#4).
Change subject: mb/ocp/tiogapass: rework GPIOs configuration using macros ......................................................................
mb/ocp/tiogapass: rework GPIOs configuration using macros
This format of PCH GPIOs configuration, unlike the raw DW0 and DW1 registers values from the inteltool dump, is more understandable and makes the code much cleaner. The gpio.h file with PAD_CFG macros was automatically generated using the util/intelp2m [1] utility:
./intelp2m -p lbg -file tiogapass/vendorbios/inteltool_gpio.log
According to the documentation [2], the Host Software Pad Ownership register only affects the pads that are configured as input (GPI). The intelp2m utility takes this into account when converting macros and ignores bits from this register for the corresponding pads.
[1] https://review.coreboot.org/c/coreboot/+/35643 [2] Intel Document Number: 549921
Change-Id: I21e98721e58b00be9196927837daa2b5d2560822 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/mainboard/ocp/tiogapass/gpio.h 1 file changed, 241 insertions(+), 241 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/40731/4
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40731 )
Change subject: mb/ocp/tiogapass: rework GPIOs configuration using macros ......................................................................
Patch Set 4:
(10 comments)
https://review.coreboot.org/c/coreboot/+/40731/4/src/mainboard/ocp/tiogapass... File src/mainboard/ocp/tiogapass/gpio.h:
https://review.coreboot.org/c/coreboot/+/40731/4/src/mainboard/ocp/tiogapass... PS4, Line 123: _PAD_CFG_STRUCT(GPP_F5, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40731/4/src/mainboard/ocp/tiogapass... PS4, Line 178: _PAD_CFG_STRUCT(GPP_C10, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_CFG0_TRIG_EDGE_BOTH | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40731/4/src/mainboard/ocp/tiogapass... PS4, Line 182: _PAD_CFG_STRUCT(GPP_C12, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40731/4/src/mainboard/ocp/tiogapass... PS4, Line 184: _PAD_CFG_STRUCT(GPP_C13, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40731/4/src/mainboard/ocp/tiogapass... PS4, Line 299: _PAD_CFG_STRUCT(GPD7, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40731/4/src/mainboard/ocp/tiogapass... PS4, Line 436: _PAD_CFG_STRUCT(GPP_G12, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40731/4/src/mainboard/ocp/tiogapass... PS4, Line 438: _PAD_CFG_STRUCT(GPP_G13, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40731/4/src/mainboard/ocp/tiogapass... PS4, Line 440: _PAD_CFG_STRUCT(GPP_G14, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40731/4/src/mainboard/ocp/tiogapass... PS4, Line 442: _PAD_CFG_STRUCT(GPP_G15, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40731/4/src/mainboard/ocp/tiogapass... PS4, Line 444: _PAD_CFG_STRUCT(GPP_G16, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), line over 96 characters
Andrey Petrov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40731 )
Change subject: mb/ocp/tiogapass: rework GPIOs configuration using macros ......................................................................
Patch Set 4: Code-Review+2
Andrey Petrov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40731 )
Change subject: mb/ocp/tiogapass: rework GPIOs configuration using macros ......................................................................
Patch Set 4: -Code-Review
(1 comment)
https://review.coreboot.org/c/coreboot/+/40731/4/src/mainboard/ocp/tiogapass... File src/mainboard/ocp/tiogapass/gpio.h:
https://review.coreboot.org/c/coreboot/+/40731/4/src/mainboard/ocp/tiogapass... PS4, Line 14: _PAD_CFG_STRUCT(GPP_A0, 0x44000102, 0x00000010), : /* GPP_A1 - LAD0 */ : _PAD_CFG_STRUCT(GPP_A1, 0x44000402, 0x00000010), : /* GPP_A2 - LAD1 */ : _PAD_CFG_STRUCT(GPP_A2, 0x44000402, 0x00000010), : /* GPP_A3 - LAD2 */ : _PAD_CFG_STRUCT(GPP_A3, 0x44000402, 0x00000010), : /* GPP_A4 - LAD3 */ : _PAD_CFG_STRUCT(GPP_A4, 0x44000402, 0x00000010), : /* GPP_A5 - LFRAME# */ : _PAD_CFG_STRUCT(GPP_A5, 0x44000600, 0x00000010), : /* GPP_A6 - SERIRQ */ : _PAD_CFG_STRUCT(GPP_A6, 0x44000502, 0x00000010), : /* GPP_A7 - PIRQA# */ : _PAD_CFG_STRUCT(GPP_A7, 0x44000502, 0x00000010), so NF1/NF3 is automatically selected based on how board is strapped, eSPI vs LPC. On TP it is LPC so NF1 is correct here. However, I don't think we need to program these at all.
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40731 )
Change subject: mb/ocp/tiogapass: rework GPIOs configuration using macros ......................................................................
Patch Set 4:
(2 comments)
https://review.coreboot.org/c/coreboot/+/40731/4/src/mainboard/ocp/tiogapass... File src/mainboard/ocp/tiogapass/gpio.h:
https://review.coreboot.org/c/coreboot/+/40731/4/src/mainboard/ocp/tiogapass... PS4, Line 14: _PAD_CFG_STRUCT(GPP_A0, 0x44000102, 0x00000010), : /* GPP_A1 - LAD0 */ : _PAD_CFG_STRUCT(GPP_A1, 0x44000402, 0x00000010), : /* GPP_A2 - LAD1 */ : _PAD_CFG_STRUCT(GPP_A2, 0x44000402, 0x00000010), : /* GPP_A3 - LAD2 */ : _PAD_CFG_STRUCT(GPP_A3, 0x44000402, 0x00000010), : /* GPP_A4 - LAD3 */ : _PAD_CFG_STRUCT(GPP_A4, 0x44000402, 0x00000010), : /* GPP_A5 - LFRAME# */ : _PAD_CFG_STRUCT(GPP_A5, 0x44000600, 0x00000010), : /* GPP_A6 - SERIRQ */ : _PAD_CFG_STRUCT(GPP_A6, 0x44000502, 0x00000010), : /* GPP_A7 - PIRQA# */ : _PAD_CFG_STRUCT(GPP_A7, 0x44000502, 0x00000010),
so NF1/NF3 is automatically selected based on how board is strapped, eSPI vs LPC. […]
Yes you are right. These NFs are set automatically after a reset. But I'm not sure, the default settings are the same as mine in this patch.
https://review.coreboot.org/c/coreboot/+/40731/4/src/mainboard/ocp/tiogapass... PS4, Line 24: RX_DISABLE We should check all the settings for the DW0 register. For example, the Tx and Rx buffer state. I think that the settings will be different, so we should leave this configuration as it is.
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40731 )
Change subject: mb/ocp/tiogapass: rework GPIOs configuration using macros ......................................................................
Patch Set 5:
(10 comments)
https://review.coreboot.org/c/coreboot/+/40731/5/src/mainboard/ocp/tiogapass... File src/mainboard/ocp/tiogapass/gpio.h:
https://review.coreboot.org/c/coreboot/+/40731/5/src/mainboard/ocp/tiogapass... PS5, Line 123: _PAD_CFG_STRUCT(GPP_F5, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40731/5/src/mainboard/ocp/tiogapass... PS5, Line 178: _PAD_CFG_STRUCT(GPP_C10, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_CFG0_TRIG_EDGE_BOTH | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40731/5/src/mainboard/ocp/tiogapass... PS5, Line 182: _PAD_CFG_STRUCT(GPP_C12, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40731/5/src/mainboard/ocp/tiogapass... PS5, Line 184: _PAD_CFG_STRUCT(GPP_C13, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40731/5/src/mainboard/ocp/tiogapass... PS5, Line 299: _PAD_CFG_STRUCT(GPD7, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40731/5/src/mainboard/ocp/tiogapass... PS5, Line 436: _PAD_CFG_STRUCT(GPP_G12, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40731/5/src/mainboard/ocp/tiogapass... PS5, Line 438: _PAD_CFG_STRUCT(GPP_G13, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40731/5/src/mainboard/ocp/tiogapass... PS5, Line 440: _PAD_CFG_STRUCT(GPP_G14, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40731/5/src/mainboard/ocp/tiogapass... PS5, Line 442: _PAD_CFG_STRUCT(GPP_G15, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40731/5/src/mainboard/ocp/tiogapass... PS5, Line 444: _PAD_CFG_STRUCT(GPP_G16, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), line over 96 characters
Andrey Petrov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40731 )
Change subject: mb/ocp/tiogapass: rework GPIOs configuration using macros ......................................................................
Patch Set 5: Code-Review+2
this has been manually tested with inteltool on TP hardware
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40731 )
Change subject: mb/ocp/tiogapass: rework GPIOs configuration using macros ......................................................................
Patch Set 5:
(2 comments)
https://review.coreboot.org/c/coreboot/+/40731/4/src/mainboard/ocp/tiogapass... File src/mainboard/ocp/tiogapass/gpio.h:
https://review.coreboot.org/c/coreboot/+/40731/4/src/mainboard/ocp/tiogapass... PS4, Line 14: _PAD_CFG_STRUCT(GPP_A0, 0x44000102, 0x00000010), : /* GPP_A1 - LAD0 */ : _PAD_CFG_STRUCT(GPP_A1, 0x44000402, 0x00000010), : /* GPP_A2 - LAD1 */ : _PAD_CFG_STRUCT(GPP_A2, 0x44000402, 0x00000010), : /* GPP_A3 - LAD2 */ : _PAD_CFG_STRUCT(GPP_A3, 0x44000402, 0x00000010), : /* GPP_A4 - LAD3 */ : _PAD_CFG_STRUCT(GPP_A4, 0x44000402, 0x00000010), : /* GPP_A5 - LFRAME# */ : _PAD_CFG_STRUCT(GPP_A5, 0x44000600, 0x00000010), : /* GPP_A6 - SERIRQ */ : _PAD_CFG_STRUCT(GPP_A6, 0x44000502, 0x00000010), : /* GPP_A7 - PIRQA# */ : _PAD_CFG_STRUCT(GPP_A7, 0x44000502, 0x00000010),
Yes you are right. These NFs are set automatically after a reset. […]
Ack
https://review.coreboot.org/c/coreboot/+/40731/4/src/mainboard/ocp/tiogapass... PS4, Line 24: RX_DISABLE
We should check all the settings for the DW0 register. […]
Ack
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40731 )
Change subject: mb/ocp/tiogapass: rework GPIOs configuration using macros ......................................................................
Patch Set 6:
(10 comments)
https://review.coreboot.org/c/coreboot/+/40731/6/src/mainboard/ocp/tiogapass... File src/mainboard/ocp/tiogapass/gpio.h:
https://review.coreboot.org/c/coreboot/+/40731/6/src/mainboard/ocp/tiogapass... PS6, Line 123: _PAD_CFG_STRUCT(GPP_F5, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40731/6/src/mainboard/ocp/tiogapass... PS6, Line 178: _PAD_CFG_STRUCT(GPP_C10, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_CFG0_TRIG_EDGE_BOTH | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40731/6/src/mainboard/ocp/tiogapass... PS6, Line 182: _PAD_CFG_STRUCT(GPP_C12, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40731/6/src/mainboard/ocp/tiogapass... PS6, Line 184: _PAD_CFG_STRUCT(GPP_C13, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40731/6/src/mainboard/ocp/tiogapass... PS6, Line 299: _PAD_CFG_STRUCT(GPD7, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40731/6/src/mainboard/ocp/tiogapass... PS6, Line 436: _PAD_CFG_STRUCT(GPP_G12, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40731/6/src/mainboard/ocp/tiogapass... PS6, Line 438: _PAD_CFG_STRUCT(GPP_G13, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40731/6/src/mainboard/ocp/tiogapass... PS6, Line 440: _PAD_CFG_STRUCT(GPP_G14, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40731/6/src/mainboard/ocp/tiogapass... PS6, Line 442: _PAD_CFG_STRUCT(GPP_G15, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40731/6/src/mainboard/ocp/tiogapass... PS6, Line 444: _PAD_CFG_STRUCT(GPP_G16, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), line over 96 characters
Hello build bot (Jenkins), Andrey Petrov,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40731
to look at the new patch set (#7).
Change subject: mb/ocp/tiogapass: rework GPIOs configuration using macros ......................................................................
mb/ocp/tiogapass: rework GPIOs configuration using macros
This format of PCH GPIOs configuration, unlike the raw DW0 and DW1 registers values from the inteltool dump, is more understandable and makes the code much cleaner. The gpio.h file with PAD_CFG macros was automatically generated using the util/intelp2m [1] utility:
./intelp2m -p lbg -file tiogapass/vendorbios/inteltool_gpio.log
According to the documentation [2], the Host Software Pad Ownership register only affects the pads that are configured as input (GPI). The intelp2m utility takes this into account when converting macros and ignores bits from this register for the corresponding pads.
[1] https://review.coreboot.org/c/coreboot/+/35643 [2] Intel Document Number: 549921
Change-Id: I21e98721e58b00be9196927837daa2b5d2560822 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/mainboard/ocp/tiogapass/gpio.h 1 file changed, 242 insertions(+), 242 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/40731/7
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40731 )
Change subject: mb/ocp/tiogapass: rework GPIOs configuration using macros ......................................................................
Patch Set 7:
(10 comments)
https://review.coreboot.org/c/coreboot/+/40731/7/src/mainboard/ocp/tiogapass... File src/mainboard/ocp/tiogapass/gpio.h:
https://review.coreboot.org/c/coreboot/+/40731/7/src/mainboard/ocp/tiogapass... PS7, Line 123: _PAD_CFG_STRUCT(GPP_F5, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40731/7/src/mainboard/ocp/tiogapass... PS7, Line 178: _PAD_CFG_STRUCT(GPP_C10, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_CFG0_TRIG_EDGE_BOTH | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40731/7/src/mainboard/ocp/tiogapass... PS7, Line 182: _PAD_CFG_STRUCT(GPP_C12, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40731/7/src/mainboard/ocp/tiogapass... PS7, Line 184: _PAD_CFG_STRUCT(GPP_C13, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40731/7/src/mainboard/ocp/tiogapass... PS7, Line 299: _PAD_CFG_STRUCT(GPD7, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40731/7/src/mainboard/ocp/tiogapass... PS7, Line 436: _PAD_CFG_STRUCT(GPP_G12, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40731/7/src/mainboard/ocp/tiogapass... PS7, Line 438: _PAD_CFG_STRUCT(GPP_G13, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40731/7/src/mainboard/ocp/tiogapass... PS7, Line 440: _PAD_CFG_STRUCT(GPP_G14, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40731/7/src/mainboard/ocp/tiogapass... PS7, Line 442: _PAD_CFG_STRUCT(GPP_G15, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40731/7/src/mainboard/ocp/tiogapass... PS7, Line 444: _PAD_CFG_STRUCT(GPP_G16, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), line over 96 characters
Andrey Petrov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40731 )
Change subject: mb/ocp/tiogapass: rework GPIOs configuration using macros ......................................................................
Patch Set 7: Code-Review+2
Andrey Petrov has submitted this change. ( https://review.coreboot.org/c/coreboot/+/40731 )
Change subject: mb/ocp/tiogapass: rework GPIOs configuration using macros ......................................................................
mb/ocp/tiogapass: rework GPIOs configuration using macros
This format of PCH GPIOs configuration, unlike the raw DW0 and DW1 registers values from the inteltool dump, is more understandable and makes the code much cleaner. The gpio.h file with PAD_CFG macros was automatically generated using the util/intelp2m [1] utility:
./intelp2m -p lbg -file tiogapass/vendorbios/inteltool_gpio.log
According to the documentation [2], the Host Software Pad Ownership register only affects the pads that are configured as input (GPI). The intelp2m utility takes this into account when converting macros and ignores bits from this register for the corresponding pads.
[1] https://review.coreboot.org/c/coreboot/+/35643 [2] Intel Document Number: 549921
Change-Id: I21e98721e58b00be9196927837daa2b5d2560822 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/40731 Reviewed-by: Andrey Petrov andrey.petrov@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/ocp/tiogapass/gpio.h 1 file changed, 242 insertions(+), 242 deletions(-)
Approvals: build bot (Jenkins): Verified Andrey Petrov: Looks good to me, approved
diff --git a/src/mainboard/ocp/tiogapass/gpio.h b/src/mainboard/ocp/tiogapass/gpio.h index 823f797..b05f536 100644 --- a/src/mainboard/ocp/tiogapass/gpio.h +++ b/src/mainboard/ocp/tiogapass/gpio.h @@ -6,539 +6,539 @@
#include <soc/gpio.h>
-/* Pad configuration */ +/* Pad configuration table for C621 Lewisburg PCH */ static const struct pad_config gpio_table[] = { /* ------- GPIO Community 0 ------- */ /* ------- GPIO Group GPP_A ------- */ /* GPP_A0 - GPIO */ - _PAD_CFG_STRUCT(GPP_A0, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_A0, NONE, DEEP, OFF, DRIVER), /* GPP_A1 - LAD0 */ - _PAD_CFG_STRUCT(GPP_A1, 0x44000402, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_A1, NONE, DEEP, NF1, NO_DISABLE, OFF), /* GPP_A2 - LAD1 */ - _PAD_CFG_STRUCT(GPP_A2, 0x44000402, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_A2, NONE, DEEP, NF1, NO_DISABLE, OFF), /* GPP_A3 - LAD2 */ - _PAD_CFG_STRUCT(GPP_A3, 0x44000402, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_A3, NONE, DEEP, NF1, NO_DISABLE, OFF), /* GPP_A4 - LAD3 */ - _PAD_CFG_STRUCT(GPP_A4, 0x44000402, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_A4, NONE, DEEP, NF1, NO_DISABLE, OFF), /* GPP_A5 - LFRAME# */ - _PAD_CFG_STRUCT(GPP_A5, 0x44000600, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_A5, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_A6 - SERIRQ */ - _PAD_CFG_STRUCT(GPP_A6, 0x44000502, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_A6, NONE, DEEP, NF1, TX_DISABLE, OFF), /* GPP_A7 - PIRQA# */ - _PAD_CFG_STRUCT(GPP_A7, 0x44000502, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_A7, NONE, DEEP, NF1, TX_DISABLE, OFF), /* GPP_A8 - CLKRUN# */ - _PAD_CFG_STRUCT(GPP_A8, 0x44000500, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_A8, NONE, DEEP, NF1, TX_DISABLE, OFF), /* GPP_A9 - CLKOUT_LPC0 */ - _PAD_CFG_STRUCT(GPP_A9, 0x44000600, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_A9, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_A10 - GPIO */ - _PAD_CFG_STRUCT(GPP_A10, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_A10, NONE, DEEP, OFF, DRIVER), /* GPP_A11 - GPIO */ - _PAD_CFG_STRUCT(GPP_A11, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_A11, NONE, DEEP, OFF, DRIVER), /* GPP_A12 - GPIO */ - _PAD_CFG_STRUCT(GPP_A12, 0x84000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_A12, NONE, PLTRST, OFF, DRIVER), /* GPP_A13 - GPIO */ - _PAD_CFG_STRUCT(GPP_A13, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_A13, NONE, DEEP, OFF, DRIVER), /* GPP_A14 - GPIO */ - _PAD_CFG_STRUCT(GPP_A14, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_A14, NONE, DEEP, OFF, DRIVER), /* GPP_A15 - GPIO */ - _PAD_CFG_STRUCT(GPP_A15, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_A15, NONE, DEEP, OFF, DRIVER), /* GPP_A16 - GPIO */ - _PAD_CFG_STRUCT(GPP_A16, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_A16, NONE, DEEP, OFF, DRIVER), /* GPP_A17 - GPIO */ - _PAD_CFG_STRUCT(GPP_A17, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_A17, NONE, DEEP, OFF, DRIVER), /* GPP_A18 - GPIO */ - _PAD_CFG_STRUCT(GPP_A18, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_A18, NONE, DEEP, OFF, DRIVER), /* GPP_A19 - RESERVED */ /* GPP_A20 - GPIO */ - _PAD_CFG_STRUCT(GPP_A20, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_A20, NONE, DEEP, OFF, DRIVER), /* GPP_A21 - GPIO */ - _PAD_CFG_STRUCT(GPP_A21, 0x44000201, 0x00000010), + PAD_CFG_GPO(GPP_A21, 1, DEEP), /* GPP_A22 - GPIO */ - _PAD_CFG_STRUCT(GPP_A22, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_A22, NONE, DEEP, OFF, DRIVER), /* GPP_A23 - GPIO */ - _PAD_CFG_STRUCT(GPP_A23, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_A23, NONE, DEEP, OFF, DRIVER),
/* ------- GPIO Group GPP_B ------- */ /* GPP_B0 - CORE_VID0 */ - _PAD_CFG_STRUCT(GPP_B0, 0x44000600, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_B0, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_B1 - CORE_VID1 */ - _PAD_CFG_STRUCT(GPP_B1, 0x44000600, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_B1, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_B2 - GPIO */ - _PAD_CFG_STRUCT(GPP_B2, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_B2, NONE, DEEP, OFF, DRIVER), /* GPP_B3 - GPIO */ - _PAD_CFG_STRUCT(GPP_B3, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_B3, NONE, DEEP, OFF, DRIVER), /* GPP_B4 - GPIO */ - _PAD_CFG_STRUCT(GPP_B4, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_B4, NONE, DEEP, OFF, DRIVER), /* GPP_B5 - GPIO */ - _PAD_CFG_STRUCT(GPP_B5, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_B5, NONE, DEEP, OFF, DRIVER), /* GPP_B6 - GPIO */ - _PAD_CFG_STRUCT(GPP_B6, 0x84000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_B6, NONE, PLTRST, OFF, DRIVER), /* GPP_B7 - GPIO */ - _PAD_CFG_STRUCT(GPP_B7, 0x84000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_B7, NONE, PLTRST, OFF, DRIVER), /* GPP_B8 - GPIO */ - _PAD_CFG_STRUCT(GPP_B8, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_B8, NONE, DEEP, OFF, DRIVER), /* GPP_B9 - GPIO */ - _PAD_CFG_STRUCT(GPP_B9, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_B9, NONE, DEEP, OFF, DRIVER), /* GPP_B10 - GPIO */ - _PAD_CFG_STRUCT(GPP_B10, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_B10, NONE, DEEP, OFF, DRIVER), /* GPP_B11 - GPIO */ - _PAD_CFG_STRUCT(GPP_B11, 0x44000201, 0x00000010), + PAD_CFG_GPO(GPP_B11, 1, DEEP), /* GPP_B12 - GLB_RST_WARN_N# */ - _PAD_CFG_STRUCT(GPP_B12, 0x44000600, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_B12, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_B13 - PLTRST# */ - _PAD_CFG_STRUCT(GPP_B13, 0x44000600, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_B13, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_B14 - SPKR */ - _PAD_CFG_STRUCT(GPP_B14, 0x44000600, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_B14, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_B15 - GPIO */ - _PAD_CFG_STRUCT(GPP_B15, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_B15, NONE, DEEP, OFF, DRIVER), /* GPP_B16 - GPIO */ - _PAD_CFG_STRUCT(GPP_B16, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_B16, NONE, DEEP, OFF, DRIVER), /* GPP_B17 - GPIO */ - _PAD_CFG_STRUCT(GPP_B17, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_B17, NONE, DEEP, OFF, DRIVER), /* GPP_B18 - GPIO */ - _PAD_CFG_STRUCT(GPP_B18, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_B18, NONE, DEEP, OFF, DRIVER), /* GPP_B19 - GPIO */ - _PAD_CFG_STRUCT(GPP_B19, 0x44000201, 0x00000010), + PAD_CFG_GPO(GPP_B19, 1, DEEP), /* GPP_B20 - GPIO */ - _PAD_CFG_STRUCT(GPP_B20, 0x44000200, 0x00000010), + PAD_CFG_GPO(GPP_B20, 0, DEEP), /* GPP_B21 - GPIO */ - _PAD_CFG_STRUCT(GPP_B21, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_B21, NONE, DEEP, OFF, DRIVER), /* GPP_B22 - GPIO */ - _PAD_CFG_STRUCT(GPP_B22, 0x44000200, 0x00000010), + PAD_CFG_GPO(GPP_B22, 0, DEEP), /* GPP_B23 - PCHHOT# */ - _PAD_CFG_STRUCT(GPP_B23, 0x00000a00, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_B23, NONE, RSMRST, NF2, RX_DISABLE, LEVEL),
/* ------- GPIO Group GPP_F ------- */ /* GPP_F0 - GPIO */ - _PAD_CFG_STRUCT(GPP_F0, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_F0, NONE, DEEP, OFF, DRIVER), /* GPP_F1 - GPIO */ - _PAD_CFG_STRUCT(GPP_F1, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_F1, NONE, DEEP, OFF, DRIVER), /* GPP_F2 - GPIO */ - _PAD_CFG_STRUCT(GPP_F2, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_F2, NONE, DEEP, OFF, DRIVER), /* GPP_F3 - GPIO */ - _PAD_CFG_STRUCT(GPP_F3, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_F3, NONE, DEEP, OFF, DRIVER), /* GPP_F4 - GPIO */ - _PAD_CFG_STRUCT(GPP_F4, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_F4, NONE, DEEP, OFF, DRIVER), /* GPP_F5 - GPIO */ - _PAD_CFG_STRUCT(GPP_F5, 0x44000101, 0x00000010), + _PAD_CFG_STRUCT(GPP_F5, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), /* GPP_F6 - GPIO */ - _PAD_CFG_STRUCT(GPP_F6, 0x84000200, 0x00000010), + PAD_CFG_GPO(GPP_F6, 0, PLTRST), /* GPP_F7 - GPIO */ - _PAD_CFG_STRUCT(GPP_F7, 0x84000200, 0x00000010), + PAD_CFG_GPO(GPP_F7, 0, PLTRST), /* GPP_F8 - GPIO */ - _PAD_CFG_STRUCT(GPP_F8, 0x84000200, 0x00000010), + PAD_CFG_GPO(GPP_F8, 0, PLTRST), /* GPP_F9 - GPIO */ - _PAD_CFG_STRUCT(GPP_F9, 0x84000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_F9, NONE, PLTRST, OFF, DRIVER), /* GPP_F10 - SATA_SCLOCK */ - _PAD_CFG_STRUCT(GPP_F10, 0x44000600, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_F10, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_F11 - SATA_SLOAD */ - _PAD_CFG_STRUCT(GPP_F11, 0x44000600, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_F11, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_F12 - GPIO */ - _PAD_CFG_STRUCT(GPP_F12, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_F12, NONE, DEEP, OFF, DRIVER), /* GPP_F13 - SATA_SDATAOUT2 */ - _PAD_CFG_STRUCT(GPP_F13, 0x44000600, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_F13, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_F14 - SSATA_LED# */ - _PAD_CFG_STRUCT(GPP_F14, 0x44000e00, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_F14, NONE, DEEP, NF3, RX_DISABLE, OFF), /* GPP_F15 - GPIO */ - _PAD_CFG_STRUCT(GPP_F15, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_F15, NONE, DEEP, OFF, DRIVER), /* GPP_F16 - GPIO */ - _PAD_CFG_STRUCT(GPP_F16, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_F16, NONE, DEEP, OFF, DRIVER), /* GPP_F17 - GPIO */ - _PAD_CFG_STRUCT(GPP_F17, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_F17, NONE, DEEP, OFF, DRIVER), /* GPP_F18 - GPIO */ - _PAD_CFG_STRUCT(GPP_F18, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_F18, NONE, DEEP, OFF, DRIVER), /* GPP_F19 - LAN_SMBCLK */ - _PAD_CFG_STRUCT(GPP_F19, 0x44000502, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_F19, NONE, DEEP, NF1, TX_DISABLE, OFF), /* GPP_F20 - LAN_SMBDATA */ - _PAD_CFG_STRUCT(GPP_F20, 0x44000502, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_F20, NONE, DEEP, NF1, TX_DISABLE, OFF), /* GPP_F21 - LAN_SMBALRT# */ - _PAD_CFG_STRUCT(GPP_F21, 0x44000602, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_F21, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_F22 - SSATA_SCLOCK */ - _PAD_CFG_STRUCT(GPP_F22, 0x44000e00, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_F22, NONE, DEEP, NF3, RX_DISABLE, OFF), /* GPP_F23 - SSATA_SLOAD */ - _PAD_CFG_STRUCT(GPP_F23, 0x44000e00, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_F23, NONE, DEEP, NF3, RX_DISABLE, OFF),
/* ------- GPIO Community 1 ------- */ /* ------- GPIO Group GPP_C ------- */ /* GPP_C0 - RESERVED */ /* GPP_C1 - RESERVED */ /* GPP_C2 - SMBALERT# */ - _PAD_CFG_STRUCT(GPP_C2, 0x44000502, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_C2, NONE, DEEP, NF1, TX_DISABLE, OFF), /* GPP_C3 - RESERVED */ /* GPP_C4 - RESERVED */ /* GPP_C5 - GPIO */ - _PAD_CFG_STRUCT(GPP_C5, 0x44000200, 0x00000000), + PAD_CFG_GPO(GPP_C5, 0, DEEP), /* GPP_C6 - RESERVED */ /* GPP_C7 - RESERVED */ /* GPP_C8 - GPIO */ - _PAD_CFG_STRUCT(GPP_C8, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_C8, NONE, DEEP, OFF, DRIVER), /* GPP_C9 - GPIO */ - _PAD_CFG_STRUCT(GPP_C9, 0x44000201, 0x00000010), + PAD_CFG_GPO(GPP_C9, 1, DEEP), /* GPP_C10 - GPIO */ - _PAD_CFG_STRUCT(GPP_C10, 0x86000103, 0x00000000), + _PAD_CFG_STRUCT(GPP_C10, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_CFG0_TRIG_EDGE_BOTH | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), /* GPP_C11 - GPIO */ - _PAD_CFG_STRUCT(GPP_C11, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_C11, NONE, DEEP, OFF, DRIVER), /* GPP_C12 - GPIO */ - _PAD_CFG_STRUCT(GPP_C12, 0x44000103, 0x00000010), + _PAD_CFG_STRUCT(GPP_C12, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), /* GPP_C13 - GPIO */ - _PAD_CFG_STRUCT(GPP_C13, 0x44000103, 0x00000010), + _PAD_CFG_STRUCT(GPP_C13, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), /* GPP_C14 - GPIO */ - _PAD_CFG_STRUCT(GPP_C14, 0x80080102, 0x00000000), + PAD_CFG_GPI_SCI(GPP_C14, NONE, PLTRST, LEVEL, NONE), /* GPP_C15 - GPIO */ - _PAD_CFG_STRUCT(GPP_C15, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_C15, NONE, DEEP, OFF, DRIVER), /* GPP_C16 - GPIO */ - _PAD_CFG_STRUCT(GPP_C16, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_C16, NONE, DEEP, OFF, DRIVER), /* GPP_C17 - GPIO */ - _PAD_CFG_STRUCT(GPP_C17, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_C17, NONE, DEEP, OFF, DRIVER), /* GPP_C18 - GPIO */ - _PAD_CFG_STRUCT(GPP_C18, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_C18, NONE, DEEP, OFF, DRIVER), /* GPP_C19 - GPIO */ - _PAD_CFG_STRUCT(GPP_C19, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_C19, NONE, DEEP, OFF, DRIVER), /* GPP_C20 - RESERVED */ /* GPP_C21 - GPIO */ - _PAD_CFG_STRUCT(GPP_C21, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_C21, NONE, DEEP, OFF, DRIVER), /* GPP_C22 - GPIO */ - _PAD_CFG_STRUCT(GPP_C22, 0x80040102, 0x00000000), + PAD_CFG_GPI_SMI(GPP_C22, NONE, PLTRST, LEVEL, NONE), /* GPP_C23 - GPIO */ - _PAD_CFG_STRUCT(GPP_C23, 0x40840102, 0x00000000), + PAD_CFG_GPI_SMI(GPP_C23, NONE, DEEP, LEVEL, INVERT),
/* ------- GPIO Group GPP_D ------- */ /* GPP_D0 - GPIO */ - _PAD_CFG_STRUCT(GPP_D0, 0x80840102, 0x00000000), + PAD_CFG_GPI_SMI(GPP_D0, NONE, PLTRST, LEVEL, INVERT), /* GPP_D1 - GPIO */ - _PAD_CFG_STRUCT(GPP_D1, 0x44000200, 0x00000010), + PAD_CFG_GPO(GPP_D1, 0, DEEP), /* GPP_D2 - GPIO */ - _PAD_CFG_STRUCT(GPP_D2, 0x84000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_D2, NONE, PLTRST, OFF, DRIVER), /* GPP_D3 - GPIO */ - _PAD_CFG_STRUCT(GPP_D3, 0x84000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_D3, NONE, PLTRST, OFF, DRIVER), /* GPP_D4 - GPIO */ - _PAD_CFG_STRUCT(GPP_D4, 0x44000201, 0x00000010), + PAD_CFG_GPO(GPP_D4, 1, DEEP), /* GPP_D5 - GPIO */ - _PAD_CFG_STRUCT(GPP_D5, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_D5, NONE, DEEP, OFF, DRIVER), /* GPP_D6 - GPIO */ - _PAD_CFG_STRUCT(GPP_D6, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_D6, NONE, DEEP, OFF, DRIVER), /* GPP_D7 - GPIO */ - _PAD_CFG_STRUCT(GPP_D7, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_D7, NONE, DEEP, OFF, DRIVER), /* GPP_D8 - GPIO */ - _PAD_CFG_STRUCT(GPP_D8, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_D8, NONE, DEEP, OFF, DRIVER), /* GPP_D9 - GPIO */ - _PAD_CFG_STRUCT(GPP_D9, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_D9, NONE, DEEP, OFF, DRIVER), /* GPP_D10 - GPIO */ - _PAD_CFG_STRUCT(GPP_D10, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_D10, NONE, DEEP, OFF, DRIVER), /* GPP_D11 - GPIO */ - _PAD_CFG_STRUCT(GPP_D11, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_D11, NONE, DEEP, OFF, DRIVER), /* GPP_D12 - GPIO */ - _PAD_CFG_STRUCT(GPP_D12, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_D12, NONE, DEEP, OFF, DRIVER), /* GPP_D13 - GPIO */ - _PAD_CFG_STRUCT(GPP_D13, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_D13, NONE, DEEP, OFF, DRIVER), /* GPP_D14 - GPIO */ - _PAD_CFG_STRUCT(GPP_D14, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_D14, NONE, DEEP, OFF, DRIVER), /* GPP_D15 - SSATA_SDATAOUT0 */ - _PAD_CFG_STRUCT(GPP_D15, 0x44000e00, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_D15, NONE, DEEP, NF3, RX_DISABLE, OFF), /* GPP_D16 - GPIO */ - _PAD_CFG_STRUCT(GPP_D16, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_D16, NONE, DEEP, OFF, DRIVER), /* GPP_D17 - GPIO */ - _PAD_CFG_STRUCT(GPP_D17, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_D17, NONE, DEEP, OFF, DRIVER), /* GPP_D18 - GPIO */ - _PAD_CFG_STRUCT(GPP_D18, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_D18, NONE, DEEP, OFF, DRIVER), /* GPP_D19 - GPIO */ - _PAD_CFG_STRUCT(GPP_D19, 0x44000201, 0x00000010), + PAD_CFG_GPO(GPP_D19, 1, DEEP), /* GPP_D20 - GPIO */ - _PAD_CFG_STRUCT(GPP_D20, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_D20, NONE, DEEP, OFF, DRIVER), /* GPP_D21 - GPIO */ - _PAD_CFG_STRUCT(GPP_D21, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_D21, NONE, DEEP, OFF, DRIVER), /* GPP_D22 - GPIO */ - _PAD_CFG_STRUCT(GPP_D22, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_D22, NONE, DEEP, OFF, DRIVER), /* GPP_D23 - GPIO */ - _PAD_CFG_STRUCT(GPP_D23, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_D23, NONE, DEEP, OFF, DRIVER),
/* ------- GPIO Group GPP_E ------- */ /* GPP_E0 - GPIO */ - _PAD_CFG_STRUCT(GPP_E0, 0x40040102, 0x00000010), + PAD_CFG_GPI_SMI(GPP_E0, NONE, DEEP, LEVEL, NONE), /* GPP_E1 - GPIO */ - _PAD_CFG_STRUCT(GPP_E1, 0x40040102, 0x00000010), + PAD_CFG_GPI_SMI(GPP_E1, NONE, DEEP, LEVEL, NONE), /* GPP_E2 - GPIO */ - _PAD_CFG_STRUCT(GPP_E2, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_E2, NONE, DEEP, OFF, DRIVER), /* GPP_E3 - CPU_GP0 */ - _PAD_CFG_STRUCT(GPP_E3, 0x44000502, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_E3, NONE, DEEP, NF1, TX_DISABLE, OFF), /* GPP_E4 - GPIO */ - _PAD_CFG_STRUCT(GPP_E4, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_E4, NONE, DEEP, OFF, DRIVER), /* GPP_E5 - GPIO */ - _PAD_CFG_STRUCT(GPP_E5, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_E5, NONE, DEEP, OFF, DRIVER), /* GPP_E6 - GPIO */ - _PAD_CFG_STRUCT(GPP_E6, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_E6, NONE, DEEP, OFF, DRIVER), /* GPP_E7 - GPIO */ - _PAD_CFG_STRUCT(GPP_E7, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_E7, NONE, DEEP, OFF, DRIVER), /* GPP_E8 - SATA_LED# */ - _PAD_CFG_STRUCT(GPP_E8, 0x44000600, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_E8, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_E9 - USB_OC0# */ - _PAD_CFG_STRUCT(GPP_E9, 0x44000502, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_E9, NONE, DEEP, NF1, TX_DISABLE, OFF), /* GPP_E10 - GPIO */ - _PAD_CFG_STRUCT(GPP_E10, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_E10, NONE, DEEP, OFF, DRIVER), /* GPP_E11 - GPIO */ - _PAD_CFG_STRUCT(GPP_E11, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_E11, NONE, DEEP, OFF, DRIVER), /* GPP_E12 - GPIO */ - _PAD_CFG_STRUCT(GPP_E12, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_E12, NONE, DEEP, OFF, DRIVER),
/* ------- GPIO Community 2 ------- */ /* -------- GPIO Group GPD -------- */ /* GPD0 - RESERVED */ /* GPD1 - GPIO */ - _PAD_CFG_STRUCT(GPD1, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPD1, NONE, RSMRST, OFF, ACPI), /* GPD2 - GPIO */ - _PAD_CFG_STRUCT(GPD2, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPD2, NONE, RSMRST, OFF, ACPI), /* GPD3 - PWRBTN# */ - _PAD_CFG_STRUCT(GPD3, 0x04000502, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPD3, NONE, RSMRST, NF1, TX_DISABLE, OFF), /* GPD4 - SLP_S3# */ - _PAD_CFG_STRUCT(GPD4, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPD4, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPD5 - SLP_S4# */ - _PAD_CFG_STRUCT(GPD5, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPD5, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPD6 - GPIO */ - _PAD_CFG_STRUCT(GPD6, 0x04000100, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPD6, NONE, RSMRST, OFF, ACPI), /* GPD7 - GPIO */ - _PAD_CFG_STRUCT(GPD7, 0x04000103, 0x00000000), + _PAD_CFG_STRUCT(GPD7, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), /* GPD8 - GPIO */ - _PAD_CFG_STRUCT(GPD8, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPD8, NONE, RSMRST, OFF, ACPI), /* GPD9 - GPIO */ - _PAD_CFG_STRUCT(GPD9, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPD9, NONE, RSMRST, OFF, ACPI), /* GPD10 - GPIO */ - _PAD_CFG_STRUCT(GPD10, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPD10, NONE, RSMRST, OFF, ACPI), /* GPD11 - GBEPHY */ - _PAD_CFG_STRUCT(GPD11, 0x04000500, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPD11, NONE, RSMRST, NF1, TX_DISABLE, OFF),
/* ------- GPIO Community 3 ------- */ /* ------- GPIO Group GPP_I ------- */ /* GPP_I0 - LAN_TDO */ - _PAD_CFG_STRUCT(GPP_I0, 0x44000900, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_I0, NONE, DEEP, NF2, TX_DISABLE, OFF), /* GPP_I1 - LAN_TCK */ - _PAD_CFG_STRUCT(GPP_I1, 0x44000a02, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_I1, NONE, DEEP, NF2, RX_DISABLE, OFF), /* GPP_I2 - LAN_TMS */ - _PAD_CFG_STRUCT(GPP_I2, 0x44000a02, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_I2, NONE, DEEP, NF2, RX_DISABLE, OFF), /* GPP_I3 - LAN_TDI */ - _PAD_CFG_STRUCT(GPP_I3, 0x44000a02, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_I3, NONE, DEEP, NF2, RX_DISABLE, OFF), /* GPP_I4 - GPIO */ - _PAD_CFG_STRUCT(GPP_I4, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_I4, NONE, DEEP, OFF, DRIVER), /* GPP_I5 - GPIO */ - _PAD_CFG_STRUCT(GPP_I5, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_I5, NONE, DEEP, OFF, DRIVER), /* GPP_I6 - GPIO */ - _PAD_CFG_STRUCT(GPP_I6, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_I6, NONE, DEEP, OFF, DRIVER), /* GPP_I7 - LAN_TRST_IN */ - _PAD_CFG_STRUCT(GPP_I7, 0x44000902, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_I7, NONE, DEEP, NF2, TX_DISABLE, OFF), /* GPP_I8 - GPIO */ - _PAD_CFG_STRUCT(GPP_I8, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_I8, NONE, DEEP, OFF, DRIVER), /* GPP_I9 - GPIO */ - _PAD_CFG_STRUCT(GPP_I9, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_I9, NONE, DEEP, OFF, DRIVER), /* GPP_I10 - GPIO */ - _PAD_CFG_STRUCT(GPP_I10, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_I10, NONE, DEEP, OFF, DRIVER),
/* ------- GPIO Community 4 ------- */ /* ------- GPIO Group GPP_J ------- */ /* GPP_J0 - LAN_LED_P0_0 */ - _PAD_CFG_STRUCT(GPP_J0, 0x44000600, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_J0, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_J1 - LAN_LED_P0_1 */ - _PAD_CFG_STRUCT(GPP_J1, 0x44000600, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_J1, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_J2 - LAN_LED_P1_0 */ - _PAD_CFG_STRUCT(GPP_J2, 0x44000600, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_J2, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_J3 - LAN_LED_P1_1 */ - _PAD_CFG_STRUCT(GPP_J3, 0x44000600, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_J3, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_J4 - LAN_LED_P2_0 */ - _PAD_CFG_STRUCT(GPP_J4, 0x44000600, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_J4, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_J5 - LAN_LED_P2_1 */ - _PAD_CFG_STRUCT(GPP_J5, 0x44000600, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_J5, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_J6 - LAN_LED_P3_0 */ - _PAD_CFG_STRUCT(GPP_J6, 0x44000600, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_J6, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_J7 - LAN_LED_P3_1 */ - _PAD_CFG_STRUCT(GPP_J7, 0x44000600, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_J7, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_J8 - LAN_I2C_SCL_MDC_P0 */ - _PAD_CFG_STRUCT(GPP_J8, 0x44000602, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_J8, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_J9 - LAN_I2C_SDA_MDIO_P0 */ - _PAD_CFG_STRUCT(GPP_J9, 0x44000402, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_J9, NONE, DEEP, NF1, NO_DISABLE, OFF), /* GPP_J10 - LAN_I2C_SCL_MDC_P1 */ - _PAD_CFG_STRUCT(GPP_J10, 0x44000602, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_J10, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_J11 - LAN_I2C_SDA_MDIO_P1 */ - _PAD_CFG_STRUCT(GPP_J11, 0x44000402, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_J11, NONE, DEEP, NF1, NO_DISABLE, OFF), /* GPP_J12 - LAN_I2C_SCL_MDC_P2 */ - _PAD_CFG_STRUCT(GPP_J12, 0x44000602, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_J12, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_J13 - LAN_I2C_SDA_MDIO_P2 */ - _PAD_CFG_STRUCT(GPP_J13, 0x44000402, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_J13, NONE, DEEP, NF1, NO_DISABLE, OFF), /* GPP_J14 - LAN_I2C_SCL_MDC_P3 */ - _PAD_CFG_STRUCT(GPP_J14, 0x44000602, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_J14, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_J15 - LAN_I2C_SDA_MDIO_P3 */ - _PAD_CFG_STRUCT(GPP_J15, 0x44000402, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_J15, NONE, DEEP, NF1, NO_DISABLE, OFF), /* GPP_J16 - LAN_SDP_P0_0 */ - _PAD_CFG_STRUCT(GPP_J16, 0x44000502, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_J16, NONE, DEEP, NF1, TX_DISABLE, OFF), /* GPP_J17 - GPIO */ - _PAD_CFG_STRUCT(GPP_J17, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_J17, NONE, DEEP, OFF, DRIVER), /* GPP_J18 - LAN_SDP_P1_0 */ - _PAD_CFG_STRUCT(GPP_J18, 0x44000502, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_J18, NONE, DEEP, NF1, TX_DISABLE, OFF), /* GPP_J19 - GPIO */ - _PAD_CFG_STRUCT(GPP_J19, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_J19, NONE, DEEP, OFF, DRIVER), /* GPP_J20 - LAN_SDP_P2_0 */ - _PAD_CFG_STRUCT(GPP_J20, 0x44000502, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_J20, NONE, DEEP, NF1, TX_DISABLE, OFF), /* GPP_J21 - GPIO */ - _PAD_CFG_STRUCT(GPP_J21, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_J21, NONE, DEEP, OFF, DRIVER), /* GPP_J22 - LAN_SDP_P3_0 */ - _PAD_CFG_STRUCT(GPP_J22, 0x44000502, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_J22, NONE, DEEP, NF1, TX_DISABLE, OFF), /* GPP_J23 - GPIO */ - _PAD_CFG_STRUCT(GPP_J23, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_J23, NONE, DEEP, OFF, DRIVER),
/* ------- GPIO Group GPP_K ------- */ /* GPP_K0 - GPIO */ - _PAD_CFG_STRUCT(GPP_K0, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_K0, NONE, DEEP, OFF, DRIVER), /* GPP_K1 - GPIO */ - _PAD_CFG_STRUCT(GPP_K1, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_K1, NONE, DEEP, OFF, DRIVER), /* GPP_K2 - GPIO */ - _PAD_CFG_STRUCT(GPP_K2, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_K2, NONE, DEEP, OFF, DRIVER), /* GPP_K3 - GPIO */ - _PAD_CFG_STRUCT(GPP_K3, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_K3, NONE, DEEP, OFF, DRIVER), /* GPP_K4 - GPIO */ - _PAD_CFG_STRUCT(GPP_K4, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_K4, NONE, DEEP, OFF, DRIVER), /* GPP_K5 - GPIO */ - _PAD_CFG_STRUCT(GPP_K5, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_K5, NONE, DEEP, OFF, DRIVER), /* GPP_K6 - GPIO */ - _PAD_CFG_STRUCT(GPP_K6, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_K6, NONE, DEEP, OFF, DRIVER), /* GPP_K7 - RESERVED */ - _PAD_CFG_STRUCT(GPP_K7, 0x44000600, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_K7, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_K8 - LAN_NCSI_ARB_IN */ - _PAD_CFG_STRUCT(GPP_K8, 0x44000502, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_K8, NONE, DEEP, NF1, TX_DISABLE, OFF), /* GPP_K9 - LAN_NCSI_ARB_OUT */ - _PAD_CFG_STRUCT(GPP_K9, 0x44000602, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_K9, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_K10 - PE_RST# */ - _PAD_CFG_STRUCT(GPP_K10, 0x44000502, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_K10, NONE, DEEP, NF1, TX_DISABLE, OFF),
/* ------- GPIO Community 5 ------- */ /* ------- GPIO Group GPP_G ------- */ /* GPP_G0 - GPIO */ - _PAD_CFG_STRUCT(GPP_G0, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_G0, NONE, DEEP, OFF, DRIVER), /* GPP_G1 - GPIO */ - _PAD_CFG_STRUCT(GPP_G1, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_G1, NONE, DEEP, OFF, DRIVER), /* GPP_G2 - GPIO */ - _PAD_CFG_STRUCT(GPP_G2, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_G2, NONE, DEEP, OFF, DRIVER), /* GPP_G3 - GPIO */ - _PAD_CFG_STRUCT(GPP_G3, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_G3, NONE, DEEP, OFF, DRIVER), /* GPP_G4 - GPIO */ - _PAD_CFG_STRUCT(GPP_G4, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_G4, NONE, DEEP, OFF, DRIVER), /* GPP_G5 - GPIO */ - _PAD_CFG_STRUCT(GPP_G5, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_G5, NONE, DEEP, OFF, DRIVER), /* GPP_G6 - GPIO */ - _PAD_CFG_STRUCT(GPP_G6, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_G6, NONE, DEEP, OFF, DRIVER), /* GPP_G7 - GPIO */ - _PAD_CFG_STRUCT(GPP_G7, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_G7, NONE, DEEP, OFF, DRIVER), /* GPP_G8 - GPIO */ - _PAD_CFG_STRUCT(GPP_G8, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_G8, NONE, DEEP, OFF, DRIVER), /* GPP_G9 - GPIO */ - _PAD_CFG_STRUCT(GPP_G9, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_G9, NONE, DEEP, OFF, DRIVER), /* GPP_G10 - GPIO */ - _PAD_CFG_STRUCT(GPP_G10, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_G10, NONE, DEEP, OFF, DRIVER), /* GPP_G11 - GPIO */ - _PAD_CFG_STRUCT(GPP_G11, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_G11, NONE, DEEP, OFF, DRIVER), /* GPP_G12 - GPIO */ - _PAD_CFG_STRUCT(GPP_G12, 0x44000103, 0x00000010), + _PAD_CFG_STRUCT(GPP_G12, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), /* GPP_G13 - GPIO */ - _PAD_CFG_STRUCT(GPP_G13, 0x44000103, 0x00000010), + _PAD_CFG_STRUCT(GPP_G13, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), /* GPP_G14 - GPIO */ - _PAD_CFG_STRUCT(GPP_G14, 0x44000101, 0x00000010), + _PAD_CFG_STRUCT(GPP_G14, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), /* GPP_G15 - GPIO */ - _PAD_CFG_STRUCT(GPP_G15, 0x44000101, 0x00000010), + _PAD_CFG_STRUCT(GPP_G15, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), /* GPP_G16 - GPIO */ - _PAD_CFG_STRUCT(GPP_G16, 0x44000101, 0x00000010), + _PAD_CFG_STRUCT(GPP_G16, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), /* GPP_G17 - ADR_COMPLETE */ - _PAD_CFG_STRUCT(GPP_G17, 0x44000600, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_G17, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_G18 - NMI# */ - _PAD_CFG_STRUCT(GPP_G18, 0x44000600, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_G18, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_G19 - SMI# */ - _PAD_CFG_STRUCT(GPP_G19, 0x44000600, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_G19, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_G20 - RESERVED */ /* GPP_G21 - GPIO */ - _PAD_CFG_STRUCT(GPP_G21, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_G21, NONE, DEEP, OFF, DRIVER), /* GPP_G22 - GPIO */ - _PAD_CFG_STRUCT(GPP_G22, 0x44000201, 0x00000010), + PAD_CFG_GPO(GPP_G22, 1, DEEP), /* GPP_G23 - GPIO */ - _PAD_CFG_STRUCT(GPP_G23, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_G23, NONE, DEEP, OFF, DRIVER),
/* ------- GPIO Group GPP_H ------- */ /* GPP_H0 - GPIO */ - _PAD_CFG_STRUCT(GPP_H0, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_H0, NONE, DEEP, OFF, DRIVER), /* GPP_H1 - GPIO */ - _PAD_CFG_STRUCT(GPP_H1, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_H1, NONE, DEEP, OFF, DRIVER), /* GPP_H2 - GPIO */ - _PAD_CFG_STRUCT(GPP_H2, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_H2, NONE, DEEP, OFF, DRIVER), /* GPP_H3 - GPIO */ - _PAD_CFG_STRUCT(GPP_H3, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_H3, NONE, DEEP, OFF, DRIVER), /* GPP_H4 - GPIO */ - _PAD_CFG_STRUCT(GPP_H4, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_H4, NONE, DEEP, OFF, DRIVER), /* GPP_H5 - RESERVED */ /* GPP_H6 - GPIO */ - _PAD_CFG_STRUCT(GPP_H6, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_H6, NONE, DEEP, OFF, DRIVER), /* GPP_H7 - GPIO */ - _PAD_CFG_STRUCT(GPP_H7, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_H7, NONE, DEEP, OFF, DRIVER), /* GPP_H8 - GPIO */ - _PAD_CFG_STRUCT(GPP_H8, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_H8, NONE, DEEP, OFF, DRIVER), /* GPP_H9 - GPIO */ - _PAD_CFG_STRUCT(GPP_H9, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_H9, NONE, DEEP, OFF, DRIVER), /* GPP_H10 - RESERVED */ /* GPP_H11 - RESERVED */ /* GPP_H12 - GPIO */ - _PAD_CFG_STRUCT(GPP_H12, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_H12, NONE, DEEP, OFF, DRIVER), /* GPP_H13 - RESERVED */ /* GPP_H14 - RESERVED */ /* GPP_H15 - GPIO */ - _PAD_CFG_STRUCT(GPP_H15, 0x84000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_H15, NONE, PLTRST, OFF, DRIVER), /* GPP_H16 - RESERVED */ /* GPP_H17 - RESERVED */ /* GPP_H18 - GPIO */ - _PAD_CFG_STRUCT(GPP_H18, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_H18, NONE, DEEP, OFF, DRIVER), /* GPP_H19 - GPIO */ - _PAD_CFG_STRUCT(GPP_H19, 0x84000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_H19, NONE, PLTRST, OFF, DRIVER), /* GPP_H20 - GPIO */ - _PAD_CFG_STRUCT(GPP_H20, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_H20, NONE, DEEP, OFF, DRIVER), /* GPP_H21 - GPIO */ - _PAD_CFG_STRUCT(GPP_H21, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_H21, NONE, DEEP, OFF, DRIVER), /* GPP_H22 - GPIO */ - _PAD_CFG_STRUCT(GPP_H22, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_H22, NONE, DEEP, OFF, DRIVER), /* GPP_H23 - GPIO */ - _PAD_CFG_STRUCT(GPP_H23, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_H23, NONE, DEEP, OFF, DRIVER),
/* ------- GPIO Group GPP_L ------- */ /* GPP_L0 - RESERVED */ /* GPP_L1 - CSME_INTR_OUT */ - _PAD_CFG_STRUCT(GPP_L1, 0x44000700, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_L1, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* GPP_L2 - GPIO */ - _PAD_CFG_STRUCT(GPP_L2, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_L2, NONE, DEEP, OFF, DRIVER), /* GPP_L3 - GPIO */ - _PAD_CFG_STRUCT(GPP_L3, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_L3, NONE, DEEP, OFF, DRIVER), /* GPP_L4 - GPIO */ - _PAD_CFG_STRUCT(GPP_L4, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_L4, NONE, DEEP, OFF, DRIVER), /* GPP_L5 - GPIO */ - _PAD_CFG_STRUCT(GPP_L5, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_L5, NONE, DEEP, OFF, DRIVER), /* GPP_L6 - GPIO */ - _PAD_CFG_STRUCT(GPP_L6, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_L6, NONE, DEEP, OFF, DRIVER), /* GPP_L7 - GPIO */ - _PAD_CFG_STRUCT(GPP_L7, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_L7, NONE, DEEP, OFF, DRIVER), /* GPP_L8 - GPIO */ - _PAD_CFG_STRUCT(GPP_L8, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_L8, NONE, DEEP, OFF, DRIVER), /* GPP_L9 - GPIO */ - _PAD_CFG_STRUCT(GPP_L9, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_L9, NONE, DEEP, OFF, DRIVER), /* GPP_L10 - GPIO */ - _PAD_CFG_STRUCT(GPP_L10, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_L10, NONE, DEEP, OFF, DRIVER), /* GPP_L11 - GPIO */ - _PAD_CFG_STRUCT(GPP_L11, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_L11, NONE, DEEP, OFF, DRIVER), /* GPP_L12 - GPIO */ - _PAD_CFG_STRUCT(GPP_L12, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_L12, NONE, DEEP, OFF, DRIVER), /* GPP_L13 - GPIO */ - _PAD_CFG_STRUCT(GPP_L13, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_L13, NONE, DEEP, OFF, DRIVER), /* GPP_L14 - GPIO */ - _PAD_CFG_STRUCT(GPP_L14, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_L14, NONE, DEEP, OFF, DRIVER), /* GPP_L15 - GPIO */ - _PAD_CFG_STRUCT(GPP_L15, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_L15, NONE, DEEP, OFF, DRIVER), /* GPP_L16 - GPIO */ - _PAD_CFG_STRUCT(GPP_L16, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_L16, NONE, DEEP, OFF, DRIVER), /* GPP_L17 - GPIO */ - _PAD_CFG_STRUCT(GPP_L17, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_L17, NONE, DEEP, OFF, DRIVER), /* GPP_L18 - GPIO */ - _PAD_CFG_STRUCT(GPP_L18, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_L18, NONE, DEEP, OFF, DRIVER), /* GPP_L19 - GPIO */ - _PAD_CFG_STRUCT(GPP_L19, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_L19, NONE, DEEP, OFF, DRIVER), };
#endif /* CFG_PCH_GPIO_H */
9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40731 )
Change subject: mb/ocp/tiogapass: rework GPIOs configuration using macros ......................................................................
Patch Set 8:
Automatic boot test returned (PASS/FAIL/TOTAL): 4/0/4 Emulation targets: "QEMU x86 q35/ich9" using payload TianoCore : SUCCESS : https://lava.9esec.io/r/3076 "QEMU x86 q35/ich9" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/3075 "QEMU x86 i440fx/piix4" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/3074 "QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/3073
Please note: This test is under development and might not be accurate at all!
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9elements QA (Code Review) -
Andrey Petrov (Code Review)
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build bot (Jenkins) (Code Review)
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Maxim Polyakov (Code Review)