[S] Change in coreboot[master]: soc/intel/cmn/cpu: Add function to disable 3-strike CATERR

[Subrata Banik (Code Review)]

Attention is currently required from: Tarun Tuli, Paul Menzel, Kapil Porwal, Ivy Jian, Eric Lai, Lean Sheng Tan, Ronak Kanabar.

Hello build bot (Jenkins), Tarun Tuli, Kapil Porwal, Ivy Jian, Eric Lai, Lean Sheng Tan, Ronak Kanabar,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/74158

to look at the new patch set (#4).

Change subject: soc/intel/cmn/cpu: Add function to disable 3-strike CATERR
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soc/intel/cmn/cpu: Add function to disable 3-strike CATERR

In Intel designs, internal processor errors, such as a processor
instruction retirement watchdog timeout (also known as a 3-strike
timeout) will cause a CATERR assertion and can only be recovered from by
a system reset.

This patch prevents the Three Strike Counter from incrementing, which
would help to disable Machine Check Catastrophic error. It will provide
more opportunity to collect more useful CPU traces for debugging.

TEST=Able to build and boot google/rex.

Signed-off-by: Subrata Banik 
Change-Id: I286037cb00603f5fbc434cd1facc5e906718ba2f
---
M src/soc/intel/common/block/cpu/cpulib.c
M src/soc/intel/common/block/include/intelblocks/cpulib.h
M src/soc/intel/common/block/include/intelblocks/msr.h
3 files changed, 38 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/74158/4