Patrick Georgi (pgeorgi@google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12603
-gerrit
commit 2460984b27945c69ffd2313625d8c340633756f7 Author: Biao Huang biao.huang@mediatek.com Date: Fri Jul 31 17:10:55 2015 +0800
mediatek/mt8173: Add GPIO driver
BUG=none TEST=emerge-oak coreboot BRANCH=none
Change-Id: I54755d81144b27cc9a674434609b2d99f1d486ec Signed-off-by: Patrick Georgi pgeorgi@chromium.org Original-Commit-Id: d88a3ed43ad32e245e54a9599fb8667ce288217b Original-Change-Id: I1142091650c0de2207c7635031aa7edfe487ad88 Original-Signed-off-by: Biao Huang biao.huang@mediatek.com Original-Reviewed-on: https://chromium-review.googlesource.com/292672 Original-Commit-Ready: Yidi Lin yidi.lin@mediatek.com Original-Tested-by: Yidi Lin yidi.lin@mediatek.com Original-Reviewed-by: Julius Werner jwerner@chromium.org --- src/soc/mediatek/mt8173/Kconfig | 1 + src/soc/mediatek/mt8173/Makefile.inc | 4 +- src/soc/mediatek/mt8173/gpio.c | 181 +++++++++++++++++++++++++++++ src/soc/mediatek/mt8173/include/soc/gpio.h | 92 +++++++++++++++ 4 files changed, 277 insertions(+), 1 deletion(-)
diff --git a/src/soc/mediatek/mt8173/Kconfig b/src/soc/mediatek/mt8173/Kconfig index 0f0b134..6f23eba 100644 --- a/src/soc/mediatek/mt8173/Kconfig +++ b/src/soc/mediatek/mt8173/Kconfig @@ -12,6 +12,7 @@ config SOC_MEDIATEK_MT8173 select HAVE_MONOTONIC_TIMER select GENERIC_UDELAY select HAS_PRECBMEM_TIMESTAMP_REGION + select GENERIC_GPIO_LIB
if SOC_MEDIATEK_MT8173
diff --git a/src/soc/mediatek/mt8173/Makefile.inc b/src/soc/mediatek/mt8173/Makefile.inc index 54b04bd..abaf3cc 100644 --- a/src/soc/mediatek/mt8173/Makefile.inc +++ b/src/soc/mediatek/mt8173/Makefile.inc @@ -28,7 +28,7 @@ ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y) bootblock-$(CONFIG_DRIVERS_UART) += uart.c endif
-bootblock-y += pmic_wrap.c +bootblock-y += gpio.c pmic_wrap.c
################################################################################
@@ -37,6 +37,7 @@ romstage-y += timer.c
romstage-$(CONFIG_DRIVERS_UART) += uart.c romstage-y += cbmem.c +romstage-y += gpio.c
################################################################################
@@ -45,6 +46,7 @@ ramstage-y += cbfs.c ramstage-y += soc.c ramstage-y += timer.c ramstage-$(CONFIG_DRIVERS_UART) += uart.c +ramstage-y += gpio.c
################################################################################
diff --git a/src/soc/mediatek/mt8173/gpio.c b/src/soc/mediatek/mt8173/gpio.c new file mode 100644 index 0000000..1f0e571 --- /dev/null +++ b/src/soc/mediatek/mt8173/gpio.c @@ -0,0 +1,181 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include <arch/io.h> +#include <assert.h> +#include <console/console.h> +#include <gpio.h> +#include <types.h> +#include <soc/addressmap.h> +#include <soc/gpio.h> + +enum { + MAX_8173_GPIO = 134, + MAX_GPIO_REG_BITS = 16, + MAX_GPIO_MODE_PER_REG = 5, + GPIO_MODE_BITS = 3, +}; + +enum { + GPIO_DIRECTION_IN = 0, + GPIO_DIRECTION_OUT = 1, +}; + +enum { + GPIO_MODE = 0, +}; + +static void pos_bit_calc(u32 pin, u32 *pos, u32 *bit) +{ + *pos = pin / MAX_GPIO_REG_BITS; + *bit = pin % MAX_GPIO_REG_BITS; +} + +static void pos_bit_calc_for_mode(u32 pin, u32 *pos, u32 *bit) +{ + *pos = pin / MAX_GPIO_MODE_PER_REG; + *bit = (pin % MAX_GPIO_MODE_PER_REG) * GPIO_MODE_BITS; +} + +static s32 gpio_set_dir(u32 pin, u32 dir) +{ + u32 pos; + u32 bit; + u16 *reg; + + assert(pin <= MAX_8173_GPIO); + + pos_bit_calc(pin, &pos, &bit); + + if (dir == GPIO_DIRECTION_IN) + reg = &mt8173_gpio->dir[pos].rst; + else + reg = &mt8173_gpio->dir[pos].set; + + write16(reg, 1L << bit); + + return 0; +} + +void gpio_set_pull(gpio_t pin, enum pull_enable enable, + enum pull_select select) +{ + u32 pos; + u32 bit; + u16 *en_reg, *sel_reg; + + assert(pin <= MAX_8173_GPIO); + + pos_bit_calc(pin, &pos, &bit); + + if (enable == GPIO_PULL_DISABLE) { + en_reg = &mt8173_gpio->pullen[pos].rst; + } else { + /* These pins' pulls can't be set through GPIO controller. */ + assert(pin < 22 || pin > 27); + assert(pin < 47 || pin > 56); + assert(pin < 57 || pin > 68); + assert(pin < 73 || pin > 78); + assert(pin < 100 || pin > 105); + assert(pin < 119 || pin > 124); + + en_reg = &mt8173_gpio->pullen[pos].set; + sel_reg = (select == GPIO_PULL_DOWN) ? + (&mt8173_gpio->pullsel[pos].rst) : + (&mt8173_gpio->pullsel[pos].set); + write16(sel_reg, 1L << bit); + } + write16(en_reg, 1L << bit); +} + +int gpio_get(gpio_t pin) +{ + u32 pos; + u32 bit; + u16 *reg; + s32 data; + + assert(pin <= MAX_8173_GPIO); + + pos_bit_calc(pin, &pos, &bit); + + reg = &mt8173_gpio->din[pos].val; + data = read32(reg); + + return (data & (1L << bit)) ? 1 : 0; +} + +void gpio_set(gpio_t pin, int output) +{ + u32 pos; + u32 bit; + u16 *reg; + + assert(pin <= MAX_8173_GPIO); + + pos_bit_calc(pin, &pos, &bit); + + if (output == 0) + reg = &mt8173_gpio->dout[pos].rst; + else + reg = &mt8173_gpio->dout[pos].set; + write16(reg, 1L << bit); +} + +void gpio_set_mode(gpio_t pin, int mode) +{ + u32 pos; + u32 bit; + u32 mask = (1L << GPIO_MODE_BITS) - 1; + + assert(pin <= MAX_8173_GPIO); + + pos_bit_calc_for_mode(pin, &pos, &bit); + + clrsetbits_le32(&mt8173_gpio->mode[pos].val, + mask << bit, mode << bit); +} + +void gpio_input_pulldown(gpio_t gpio) +{ + gpio_set_pull(gpio, GPIO_PULL_ENABLE, GPIO_PULL_DOWN); + gpio_set_dir(gpio, GPIO_DIRECTION_IN); + gpio_set_mode(gpio, GPIO_MODE); +} + +void gpio_input_pullup(gpio_t gpio) +{ + gpio_set_pull(gpio, GPIO_PULL_ENABLE, GPIO_PULL_UP); + gpio_set_dir(gpio, GPIO_DIRECTION_IN); + gpio_set_mode(gpio, GPIO_MODE); +} + +void gpio_input(gpio_t gpio) +{ + gpio_set_pull(gpio, GPIO_PULL_DISABLE, GPIO_PULL_DOWN); + gpio_set_dir(gpio, GPIO_DIRECTION_IN); + gpio_set_mode(gpio, GPIO_MODE); +} + +void gpio_output(gpio_t gpio, int value) +{ + gpio_set_pull(gpio, GPIO_PULL_DISABLE, GPIO_PULL_DOWN); + gpio_set(gpio, value); + gpio_set_dir(gpio, GPIO_DIRECTION_OUT); + gpio_set_mode(gpio, GPIO_MODE); +} diff --git a/src/soc/mediatek/mt8173/include/soc/gpio.h b/src/soc/mediatek/mt8173/include/soc/gpio.h new file mode 100644 index 0000000..d0a3dd2 --- /dev/null +++ b/src/soc/mediatek/mt8173/include/soc/gpio.h @@ -0,0 +1,92 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#ifndef SOC_MEDIATEK_MT8173_GPIO_H +#define SOC_MEDIATEK_MT8173_GPIO_H + +#include <stdint.h> +#include <stdlib.h> +#include <soc/addressmap.h> + +enum pull_enable { + GPIO_PULL_DISABLE = 0, + GPIO_PULL_ENABLE = 1, +}; + +enum pull_select { + GPIO_PULL_DOWN = 0, + GPIO_PULL_UP = 1, +}; + +enum external_power { + GPIO_EINT_3P3V = 0, + GPIO_EINT_1P8V = 1, +}; + +typedef u32 gpio_t; + +struct val_regs { + uint16_t val; + uint16_t align1; + uint16_t set; + uint16_t align2; + uint16_t rst; + uint16_t align3[3]; +}; + +struct gpio_regs { + struct val_regs dir[9]; + uint8_t rsv00[112]; + struct val_regs pullen[9]; + uint8_t rsv01[112]; + struct val_regs pullsel[9]; + uint8_t rsv02[112]; + uint8_t rsv03[256]; + struct val_regs dout[9]; + uint8_t rsv04[112]; + struct val_regs din[9]; + uint8_t rsv05[112]; + struct val_regs mode[27]; + uint8_t rsv06[336]; + struct val_regs ies[3]; + struct val_regs smt[3]; + uint8_t rsv07[160]; + struct val_regs tdsel[8]; + struct val_regs rdsel[6]; + uint8_t rsv08[32]; + struct val_regs drv_mode[10]; + uint8_t rsv09[96]; + struct val_regs msdc_rsv0[11]; + struct val_regs msdc2_ctrl5; + struct val_regs msdc_rsv1[12]; + uint8_t rsv10[64]; + struct val_regs exmd_ctrl[1]; + uint8_t rsv11[48]; + struct val_regs kpad_ctrl[2]; + struct val_regs hsic_ctrl[4]; +}; + +check_member(gpio_regs, msdc2_ctrl5, 0xcb0); +check_member(gpio_regs, hsic_ctrl[3], 0xe50); + +static struct gpio_regs *const mt8173_gpio = (void *)(GPIO_BASE); + +void gpio_set_pull(gpio_t gpio, enum pull_enable enable, + enum pull_select select); +void gpio_set_mode(gpio_t gpio, int mode); +#endif /* SOC_MEDIATEK_MT8173_GPIO_H */
-
Patrick Georgi