[XS] Change in coreboot[main]: soc/mediatek/mt8196: Remove tvdpll3 disable/enable

[Jarried Lin (Code Review)]

Attention is currently required from: Hung-Te Lin, Yidi Lin, Yu-Ping Wu.

Jarried Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86343?usp=email )

Change subject: soc/mediatek/mt8196: Remove tvdpll3 disable/enable
......................................................................

soc/mediatek/mt8196: Remove tvdpll3 disable/enable

The enable operation cause tvdpll3 cannot be disabled during suspend,
so we remove it.
tvdpll3 can be enabled/disabled according to its downstream clock
demand automatically.

BRANCH=rauru
BUG=b:377628718
TEST=Bootup OK and Suspend/Resume OK, with MMinfra kernel/vcp patch,
mminfra can be turned off to reduce power consumption.

Signed-off-by: Guangjie Song 
Change-Id: Ib9c72a1602c1f76dc94cca5c4a61a542a853560b
---
M src/soc/mediatek/mt8196/pll.c
1 file changed, 0 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/86343/1

diff --git a/src/soc/mediatek/mt8196/pll.c b/src/soc/mediatek/mt8196/pll.c
index 59a9b09..2007197 100644
--- a/src/soc/mediatek/mt8196/pll.c
+++ b/src/soc/mediatek/mt8196/pll.c
@@ -1572,11 +1572,7 @@
 {
    const struct pll *pll = &plls[CLK_APMIXED2_TVDPLL3];

-	clrbits32(pll->reg, MT8196_PLL_EN);
    pll_set_rate(pll, freq);
-	setbits32(pll->reg, MT8196_PLL_EN);
-
-	udelay(PLL_EN_DELAY);
 }

void mt_pll_edp_mux_set_sel(u32 sel)