Change in coreboot[master]: intel/fsp_rangeley: Avoid preprocessor with HAVE_SMI_HANDLER

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34253 )

Change subject: intel/fsp_rangeley: Avoid preprocessor with HAVE_SMI_HANDLER
......................................................................

intel/fsp_rangeley: Avoid preprocessor with HAVE_SMI_HANDLER

Change-Id: Id9abc239a92fa7d3e29738f08f2ccdaf3232dfb6
Signed-off-by: Kyösti Mälkki 
---
M src/southbridge/intel/fsp_rangeley/acpi.c
M src/southbridge/intel/fsp_rangeley/lpc.c
2 files changed, 3 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/34253/1

diff --git a/src/southbridge/intel/fsp_rangeley/acpi.c b/src/southbridge/intel/fsp_rangeley/acpi.c
index e0b3cb9..aeb2d9b 100644
--- a/src/southbridge/intel/fsp_rangeley/acpi.c
+++ b/src/southbridge/intel/fsp_rangeley/acpi.c
@@ -23,9 +23,6 @@
 #include <device/pci_ops.h>
 #include <version.h>

-#if CONFIG(HAVE_SMI_HANDLER)
-#include <cpu/x86/smm.h>
-#endif

/**
  * Fill in the FADT with generic values that can be overridden later.
diff --git a/src/southbridge/intel/fsp_rangeley/lpc.c b/src/southbridge/intel/fsp_rangeley/lpc.c
index ba5e04b..af2e4115 100644
--- a/src/southbridge/intel/fsp_rangeley/lpc.c
+++ b/src/southbridge/intel/fsp_rangeley/lpc.c
@@ -421,10 +421,10 @@
    if (gnvs) {
    	memset(gnvs, 0, sizeof(*gnvs));
    	acpi_create_gnvs(gnvs);
-#if CONFIG(HAVE_SMI_HANDLER)
+
    	/* And tell SMI about it */
-		smm_setup_structures(gnvs, NULL, NULL);
-#endif
+		if (CONFIG(HAVE_SMI_HANDLER))
+			smm_setup_structures(gnvs, NULL, NULL);

/* Add it to DSDT.  */
    	acpigen_write_scope("\");

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34253 )

Change subject: intel/fsp_rangeley: Avoid preprocessor with HAVE_SMI_HANDLER
......................................................................

Patch Set 1: Code-Review+2

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/34253 )

Change subject: intel/fsp_rangeley: Avoid preprocessor with HAVE_SMI_HANDLER
......................................................................

intel/fsp_rangeley: Avoid preprocessor with HAVE_SMI_HANDLER

Change-Id: Id9abc239a92fa7d3e29738f08f2ccdaf3232dfb6
Signed-off-by: Kyösti Mälkki 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34253
Tested-by: build bot (Jenkins) 
Reviewed-by: Angel Pons 
---
M src/southbridge/intel/fsp_rangeley/acpi.c
M src/southbridge/intel/fsp_rangeley/lpc.c
2 files changed, 3 insertions(+), 6 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Angel Pons: Looks good to me, approved

diff --git a/src/southbridge/intel/fsp_rangeley/acpi.c b/src/southbridge/intel/fsp_rangeley/acpi.c
index e0b3cb9..aeb2d9b 100644
--- a/src/southbridge/intel/fsp_rangeley/acpi.c
+++ b/src/southbridge/intel/fsp_rangeley/acpi.c
@@ -23,9 +23,6 @@
 #include <device/pci_ops.h>
 #include <version.h>

-#if CONFIG(HAVE_SMI_HANDLER)
-#include <cpu/x86/smm.h>
-#endif

/**
  * Fill in the FADT with generic values that can be overridden later.
diff --git a/src/southbridge/intel/fsp_rangeley/lpc.c b/src/southbridge/intel/fsp_rangeley/lpc.c
index ba5e04b..af2e4115 100644
--- a/src/southbridge/intel/fsp_rangeley/lpc.c
+++ b/src/southbridge/intel/fsp_rangeley/lpc.c
@@ -421,10 +421,10 @@
    if (gnvs) {
    	memset(gnvs, 0, sizeof(*gnvs));
    	acpi_create_gnvs(gnvs);
-#if CONFIG(HAVE_SMI_HANDLER)
+
    	/* And tell SMI about it */
-		smm_setup_structures(gnvs, NULL, NULL);
-#endif
+		if (CONFIG(HAVE_SMI_HANDLER))
+			smm_setup_structures(gnvs, NULL, NULL);

/* Add it to DSDT.  */
    	acpigen_write_scope("\");

[David Guckian (Code Review)]

David Guckian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34253 )

Change subject: intel/fsp_rangeley: Avoid preprocessor with HAVE_SMI_HANDLER
......................................................................

Patch Set 2: Code-Review+1