Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35128 )
Change subject: ec/google/chromeec: Add config option for eSPI ......................................................................
ec/google/chromeec: Add config option for eSPI
The Intel platforms using eSPI EC communication have just been enabling the EC_GOOGLE_CHROMEEC_LPC option for simplicity. This does basically the same, but at least marks it as eSPI in Kconfig for clarity.
BUG=b:140055300 TEST=Build tested only.
Change-Id: Ib56ec9d1dc204809a05c846494ff0e0d69cf70ea Signed-off-by: Martin Roth martinroth@google.com --- M src/ec/google/chromeec/Kconfig 1 file changed, 10 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/35128/1
diff --git a/src/ec/google/chromeec/Kconfig b/src/ec/google/chromeec/Kconfig index 3eb2c48..8c7d24e 100644 --- a/src/ec/google/chromeec/Kconfig +++ b/src/ec/google/chromeec/Kconfig @@ -47,6 +47,16 @@ help Use only proto3 for i2c EC communication.
+config EC_GOOGLE_CHROMEEC_ESPI + depends on EC_GOOGLE_CHROMEEC && ARCH_X86 # Needs Plug-and-play. + def_bool n + select EC_GOOGLE_CHROMEEC_LPC + help + Google Chrome EC via eSPI bus. + The EC communication code is the same between eSPI and LPC, so + this option simply enables the LPC EC code. The eSPI device + still needs to correctly configure the bus transactions. + config EC_GOOGLE_CHROMEEC_LPC depends on EC_GOOGLE_CHROMEEC && ARCH_X86 # Needs Plug-and-play. def_bool y
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35128 )
Change subject: ec/google/chromeec: Add config option for eSPI ......................................................................
Patch Set 1: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/35128/1/src/ec/google/chromeec/Kcon... File src/ec/google/chromeec/Kconfig:
https://review.coreboot.org/c/coreboot/+/35128/1/src/ec/google/chromeec/Kcon... PS1, Line 55: Google Chrome EC via eSPI bus. Add blank line below?
Hello Paul Menzel, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35128
to look at the new patch set (#2).
Change subject: ec/google/chromeec: Add config option for eSPI ......................................................................
ec/google/chromeec: Add config option for eSPI
The Intel platforms using eSPI EC communication have just been enabling the EC_GOOGLE_CHROMEEC_LPC option for simplicity. This does basically the same, but at least marks it as eSPI in Kconfig for clarity.
BUG=b:140055300 TEST=Build tested only.
Change-Id: Ib56ec9d1dc204809a05c846494ff0e0d69cf70ea Signed-off-by: Martin Roth martinroth@google.com --- M src/ec/google/chromeec/Kconfig 1 file changed, 11 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/35128/2
Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35128 )
Change subject: ec/google/chromeec: Add config option for eSPI ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35128/1/src/ec/google/chromeec/Kcon... File src/ec/google/chromeec/Kconfig:
https://review.coreboot.org/c/coreboot/+/35128/1/src/ec/google/chromeec/Kcon... PS1, Line 55: Google Chrome EC via eSPI bus.
Add blank line below?
Done
Mathew King has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35128 )
Change subject: ec/google/chromeec: Add config option for eSPI ......................................................................
Patch Set 2: Code-Review+1
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35128 )
Change subject: ec/google/chromeec: Add config option for eSPI ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35128/2/src/ec/google/chromeec/Kcon... File src/ec/google/chromeec/Kconfig:
https://review.coreboot.org/c/coreboot/+/35128/2/src/ec/google/chromeec/Kcon... PS2, Line 63: def_bool y But it's already defaulted to y. If we're going to add the Kconfig shouldn't we be selecting it for the mainboards where it applies? This does provide a path for clarity, but I don't see any back-filling taking place in follow up CLs.
Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35128 )
Change subject: ec/google/chromeec: Add config option for eSPI ......................................................................
Patch Set 3:
(1 comment)
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35128/2/src/ec/google/chromeec/Kcon... File src/ec/google/chromeec/Kconfig:
https://review.coreboot.org/c/coreboot/+/35128/2/src/ec/google/chromeec/Kcon... PS2, Line 63: def_bool y
But it's already defaulted to y. […]
Added follow-on commits to update existing mainboards and default this to disabled.
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35128 )
Change subject: ec/google/chromeec: Add config option for eSPI ......................................................................
Patch Set 3: Code-Review+2
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35128 )
Change subject: ec/google/chromeec: Add config option for eSPI ......................................................................
Patch Set 3: Code-Review+2
Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/35128 )
Change subject: ec/google/chromeec: Add config option for eSPI ......................................................................
ec/google/chromeec: Add config option for eSPI
The Intel platforms using eSPI EC communication have just been enabling the EC_GOOGLE_CHROMEEC_LPC option for simplicity. This does basically the same, but at least marks it as eSPI in Kconfig for clarity.
BUG=b:140055300 TEST=Build tested only.
Change-Id: Ib56ec9d1dc204809a05c846494ff0e0d69cf70ea Signed-off-by: Martin Roth martinroth@google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/35128 Reviewed-by: Aaron Durbin adurbin@chromium.org Reviewed-by: Furquan Shaikh furquan@google.com Reviewed-by: Mathew King mathewk@chromium.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/ec/google/chromeec/Kconfig 1 file changed, 11 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Aaron Durbin: Looks good to me, approved Furquan Shaikh: Looks good to me, approved Mathew King: Looks good to me, but someone else must approve
diff --git a/src/ec/google/chromeec/Kconfig b/src/ec/google/chromeec/Kconfig index 3eb2c48..2242653 100644 --- a/src/ec/google/chromeec/Kconfig +++ b/src/ec/google/chromeec/Kconfig @@ -47,6 +47,17 @@ help Use only proto3 for i2c EC communication.
+config EC_GOOGLE_CHROMEEC_ESPI + depends on EC_GOOGLE_CHROMEEC && ARCH_X86 # Needs Plug-and-play. + def_bool n + select EC_GOOGLE_CHROMEEC_LPC + help + Google Chrome EC via eSPI bus. + + The EC communication code is the same between eSPI and LPC, so + this option simply enables the LPC EC code. The eSPI device + still needs to correctly configure the bus transactions. + config EC_GOOGLE_CHROMEEC_LPC depends on EC_GOOGLE_CHROMEEC && ARCH_X86 # Needs Plug-and-play. def_bool y
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Aaron Durbin (Code Review) -
Furquan Shaikh (Code Review)
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Martin Roth (Code Review)
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Mathew King (Code Review)
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Patrick Georgi (Code Review)
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Paul Menzel (Code Review)