Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69980 )
Change subject: sb/intel: Use "sb/intel/common/tco.h" macros ......................................................................
sb/intel: Use "sb/intel/common/tco.h" macros
Also use read_pmbase{16,32}() in bd82x6x/elog.c.
Change-Id: Ie8e6d4817ea706fc7058ec15893afb0168c1a2cb Signed-off-by: Elyes Haouas ehaouas@noos.fr --- M src/southbridge/intel/bd82x6x/elog.c M src/southbridge/intel/common/finalize.c M src/southbridge/intel/common/pmutil.c M src/southbridge/intel/common/pmutil.h M src/southbridge/intel/common/tco.h M src/southbridge/intel/i82801ix/early_init.c M src/southbridge/intel/i82801jx/early_init.c 7 files changed, 44 insertions(+), 28 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/69980/1
diff --git a/src/southbridge/intel/bd82x6x/elog.c b/src/southbridge/intel/bd82x6x/elog.c index 684f830..ec1f71c 100644 --- a/src/southbridge/intel/bd82x6x/elog.c +++ b/src/southbridge/intel/bd82x6x/elog.c @@ -1,13 +1,15 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#include <arch/io.h> #include <acpi/acpi.h> +#include <arch/io.h> #include <device/device.h> -#include <device/pci.h> #include <device/pci_ops.h> -#include <stdint.h> +#include <device/pci.h> #include <elog.h> +#include <southbridge/intel/common/pmbase.h> #include <southbridge/intel/common/pmutil.h> +#include <stdint.h> + #include "pch.h"
void pch_log_state(void) @@ -20,10 +22,10 @@ if (!lpc) return;
- pm1_sts = inw(DEFAULT_PMBASE + PM1_STS); - gpe0_sts = inl(DEFAULT_PMBASE + GPE0_STS); - gpe0_en = inl(DEFAULT_PMBASE + GPE0_EN); - tco2_sts = inw(DEFAULT_PMBASE + TCO2_STS); + pm1_sts = read_pmbase16(PM1_STS); + gpe0_sts = read_pmbase32(GPE0_STS); + gpe0_en = read_pmbase32(GPE0_EN); + tco2_sts = read_pmbase16(PMBASE_TCO_OFFSET + TCO2_STS); gen_pmcon_2 = pci_read_config8(lpc, GEN_PMCON_2); gen_pmcon_3 = pci_read_config16(lpc, GEN_PMCON_3);
diff --git a/src/southbridge/intel/common/finalize.c b/src/southbridge/intel/common/finalize.c index 6fb27bb..4b27ceb 100644 --- a/src/southbridge/intel/common/finalize.c +++ b/src/southbridge/intel/common/finalize.c @@ -5,6 +5,8 @@ #include <southbridge/intel/common/pmbase.h> #include <southbridge/intel/common/pmutil.h> #include <southbridge/intel/common/rcba.h> +#include <southbridge/intel/common/tco.h> + #include <spi-generic.h>
#include "finalize.h" @@ -48,7 +50,8 @@ if (CONFIG(BOOTMEDIA_SMM_BWP)) write_pmbase16(SMI_EN, read_pmbase16(SMI_EN) | TCO_EN);
- write_pmbase16(TCO1_CNT, read_pmbase16(TCO1_CNT) | TCO_LOCK); + write_pmbase16(PMBASE_TCO_OFFSET + TCO1_CNT, + read_pmbase16(PMBASE_TCO_OFFSET + TCO1_CNT) | TCO_LOCK);
post_code(POST_OS_BOOT); } diff --git a/src/southbridge/intel/common/pmutil.c b/src/southbridge/intel/common/pmutil.c index 8ecb74c..c89dc9f 100644 --- a/src/southbridge/intel/common/pmutil.c +++ b/src/southbridge/intel/common/pmutil.c @@ -1,10 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#include <types.h> #include <console/console.h> #include <device/pci_def.h> -#include <southbridge/intel/common/pmbase.h> #include <southbridge/intel/common/gpio.h> +#include <southbridge/intel/common/pmbase.h> +#include <southbridge/intel/common/tco.h> +#include <types.h>
#include "pmutil.h"
@@ -148,14 +149,14 @@ { u32 reg32;
- reg32 = read_pmbase32(TCO1_STS); + reg32 = read_pmbase32(PMBASE_TCO_OFFSET + TCO1_STS); /* * set status bits are cleared by writing 1 to them, but don't * clear BOOT_STS before SECOND_TO_STS. */ - write_pmbase32(TCO1_STS, reg32 & ~BOOT_STS); + write_pmbase32(PMBASE_TCO_OFFSET + TCO2_STS, reg32 & ~BOOT_STS); if (reg32 & BOOT_STS) - write_pmbase32(TCO1_STS, BOOT_STS); + write_pmbase32(PMBASE_TCO_OFFSET + TCO2_STS, BOOT_STS);
return reg32; } diff --git a/src/southbridge/intel/common/pmutil.h b/src/southbridge/intel/common/pmutil.h index 5cf76b6..a9edcd8 100644 --- a/src/southbridge/intel/common/pmutil.h +++ b/src/southbridge/intel/common/pmutil.h @@ -104,14 +104,6 @@ #define GPE_CNTL 0x42 #define DEVACT_STS 0x44
-#define TCO1_STS 0x64 -#define DMISCI_STS (1 << 9) -#define BOOT_STS (1 << 18) -#define TCO2_STS 0x66 -#define TCO1_CNT 0x68 -#define TCO_LOCK (1 << 12) -#define TCO2_CNT 0x6a - u16 get_pmbase(void);
u16 reset_pm1_status(void); diff --git a/src/southbridge/intel/common/tco.h b/src/southbridge/intel/common/tco.h index 03d3122..4690320 100644 --- a/src/southbridge/intel/common/tco.h +++ b/src/southbridge/intel/common/tco.h @@ -6,9 +6,13 @@ #define PMBASE_TCO_OFFSET 0x60 #define TCO1_STS 0x04 #define TCO1_TIMEOUT (1 << 3) +#define DMISCI_STS (1 << 9) #define TCO2_STS 0x06 #define SECOND_TO_STS (1 << 1) +#define BOOT_STS (1 << 2) #define TCO1_CNT 0x08 #define TCO_TMR_HLT (1 << 11) +#define TCO_LOCK (1 << 12) +#define TCO2_CNT 0x0a
#endif /* SOUTHBRIDGE_INTEL_COMMON_TCO_H */ diff --git a/src/southbridge/intel/i82801ix/early_init.c b/src/southbridge/intel/i82801ix/early_init.c index b8bc9d8..34717b99 100644 --- a/src/southbridge/intel/i82801ix/early_init.c +++ b/src/southbridge/intel/i82801ix/early_init.c @@ -4,6 +4,8 @@ #include <device/pci_ops.h> #include <device/smbus_host.h> #include <southbridge/intel/common/pmutil.h> +#include <southbridge/intel/common/tco.h> + #include "i82801ix.h" #include "chip.h"
@@ -64,8 +66,8 @@ pci_or_config8(d31f0, D31F0_GPIO_CNTL, 0x10);
/* Reset watchdog. */ - outw(0x0008, DEFAULT_TCOBASE + 0x04); /* R/WC, clear TCO caused SMI. */ - outw(0x0002, DEFAULT_TCOBASE + 0x06); /* R/WC, clear second timeout. */ + write_pmbase16(PMBASE_TCO_OFFSET + TCO1_STS, TCO1_TIMEOUT); + write_pmbase16(PMBASE_TCO_OFFSET + TCO2_STS, SECOND_TO_STS);
/* Enable upper 128bytes of CMOS. */ RCBA32(0x3400) = (1 << 2); diff --git a/src/southbridge/intel/i82801jx/early_init.c b/src/southbridge/intel/i82801jx/early_init.c index f7e880c..b79b352 100644 --- a/src/southbridge/intel/i82801jx/early_init.c +++ b/src/southbridge/intel/i82801jx/early_init.c @@ -6,6 +6,8 @@ #include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/pmbase.h> #include <southbridge/intel/common/pmutil.h> +#include <southbridge/intel/common/tco.h> + #include "i82801jx.h" #include "chip.h"
@@ -63,8 +65,6 @@ pci_or_config8(d31f0, D31F0_GPIO_CNTL, 0x10); }
-#define TCO_BASE 0x60 - void i82801jx_early_init(void) { const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0); @@ -80,9 +80,9 @@
printk(BIOS_DEBUG, "Disabling Watchdog reboot..."); RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */ - write_pmbase16(TCO_BASE + 0x8, (1 << 11)); /* halt timer */ - write_pmbase16(TCO_BASE + 0x4, (1 << 3)); /* clear timeout */ - write_pmbase16(TCO_BASE + 0x6, (1 << 1)); /* clear 2nd timeout */ + write_pmbase16(PMBASE_TCO_OFFSET + TCO1_CNT, TCO_TMR_HLT); + write_pmbase16(PMBASE_TCO_OFFSET + TCO1_STS, TCO1_TIMEOUT); + write_pmbase16(PMBASE_TCO_OFFSET + TCO2_STS, SECOND_TO_STS); printk(BIOS_DEBUG, " done.\n");
/* Enable IOAPIC */
-
Elyes Haouas (Code Review)