Attention is currently required from: Hung-Te Lin, Jarried Lin.
Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/86551?usp=email )
Change subject: soc/mediatek/mt8196: Save HW protect temperature to SRAM ......................................................................
Patch Set 2:
(5 comments)
File src/soc/mediatek/mt8196/thermal.c:
https://review.coreboot.org/c/coreboot/+/86551/comment/709a3bae_07ac3074?usp... : PS2, Line 606: if (tc_num == LVTS_AP_CONTROLLER0) : tc_index = 0; : else if (tc_num == LVTS_AP_CONTROLLER1) : tc_index = 1; : : if (tc_index != 0xff) { : thermal_write_reboot_msr_sram(tc_index, raw_high); : if (tc_index == 0) : thermal_write_reboot_temp_sram(tc->reboot_temperature); : }
I feel like the flow should be controlled by the `lvts_thermal_controller` struct, because that's how the remaining code works. Can we add a new bit field `flags` to indicate whether `thermal_write_reboot_*_sram` needs to be called?
Right now only controllers 0 and 1 are enabled (`CTRL_ON`). However the code here should support controllers 2 and 3 as well. Should `thermal_write_reboot_msr_sram` and `thermal_write_reboot_temp_sram` be called for controllers 2 and 3 (if they are enabled)?
File src/soc/mediatek/mt8196/thermal_sram.c:
https://review.coreboot.org/c/coreboot/+/86551/comment/4734ff0a_80b8a36d?usp... : PS2, Line 10: c C
https://review.coreboot.org/c/coreboot/+/86551/comment/66205ec1_8591d7e0?usp... : PS2, Line 66: int uint32_t
https://review.coreboot.org/c/coreboot/+/86551/comment/07e087ce_37c27bda?usp... : PS2, Line 71: int
unint32_t ?
`unsigned int` IMO
https://review.coreboot.org/c/coreboot/+/86551/comment/a6c053e9_adda6025?usp... : PS2, Line 74: if ((idx * 4) < THERMAL_REBOOT_MSR_SRAM_LEN) { If `idx * 4 >= THERMAL_REBOOT_MSR_SRAM_LEN` is an unexpected case, can we use an assertion?