[S] Change in coreboot[master]: soc/intel/alderlake: Disable L1 substates for PCIe compliance test mode

[Bora Guvendik (Code Review)]

Attention is currently required from: Bora Guvendik.

Hello Bora Guvendik,

I'd like you to do a code review.
Please visit

https://review.coreboot.org/c/coreboot/+/70165

to review the following change.

Change subject: soc/intel/alderlake: Disable L1 substates for PCIe compliance test mode
......................................................................

soc/intel/alderlake: Disable L1 substates for PCIe compliance test mode

Disable L1 substates for PCIe compliance test mode in order to get
continous clock output.

BUG=b:235863379
TEST=Boot in compliance mode, check FSP settings

Signed-off-by: Bora Guvendik 
Change-Id: I2a3b313425e00fe11f616d964f825baaef463c71
---
M src/soc/intel/alderlake/fsp_params.c
1 file changed, 19 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/70165/1

diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index 853b2f2..224cf8a 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -471,7 +471,9 @@
  */
 static int get_l1_substate_control(enum L1_substates_control ctl)
 {
-	if ((ctl > L1_SS_L1_2) || (ctl == L1_SS_FSP_DEFAULT))
+	if (CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE))
+		ctl = L1_SS_DISABLED;
+	else if ((ctl > L1_SS_L1_2) || (ctl == L1_SS_FSP_DEFAULT))
    	ctl = L1_SS_L1_2;
    return ctl - 1;
 }