Change in coreboot[master]: soc/amd/cezanne: Clear eSPI ranges before configuring eSPI

[Raul Rangel (Code Review)]

Raul Rangel has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51749 )

Change subject: soc/amd/cezanne: Clear eSPI ranges before configuring eSPI
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soc/amd/cezanne: Clear eSPI ranges before configuring eSPI

The Cezanne PSP configures the eSPI with the assumption that it's a
majolica, setting up both the serial port and the majolica EC IO decode
ranges.  Since guybrush is NOT a majolica, this doesn't work very well
there.  Clearing the decode ranges allows the guybrush platform to set
the decode ranges needed for its EC.

BUG=b:183524609
TEST=Set up eSPI on Guybrush

Signed-off-by: Martin Roth 
Change-Id: I77cfb948cb9ae6d1cf001bd9e66cede8d93f50b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51749
Tested-by: build bot (Jenkins) 
Reviewed-by: Raul Rangel 
Reviewed-by: Marshall Dawson 
Reviewed-by: Furquan Shaikh 
---
M src/soc/amd/cezanne/early_fch.c
1 file changed, 1 insertion(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Furquan Shaikh: Looks good to me, approved
  Marshall Dawson: Looks good to me, approved
  Raul Rangel: Looks good to me, approved

diff --git a/src/soc/amd/cezanne/early_fch.c b/src/soc/amd/cezanne/early_fch.c
index 0c72863..acd2a7a 100644
--- a/src/soc/amd/cezanne/early_fch.c
+++ b/src/soc/amd/cezanne/early_fch.c
@@ -68,6 +68,7 @@
    	lpc_disable_spi_rom_sharing();

if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI)) {
+		espi_clear_decodes();
    	espi_setup();
    	espi_configure_decodes();
    }