Change in coreboot[master]: sb/intel/bd82x6x/early_usb: Use register name

[Patrick Rudolph (Code Review)]

Patrick Rudolph has uploaded a new change for review. ( https://review.coreboot.org/19954 )

Change subject: sb/intel/bd82x6x/early_usb: Use register name
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sb/intel/bd82x6x/early_usb: Use register name

Use register name instead of magic value.

Change-Id: I4f2f3f196c12489613333ab9f6098443edda927f
Signed-off-by: Patrick Rudolph 
---
M src/southbridge/intel/bd82x6x/early_usb.c
M src/southbridge/intel/bd82x6x/pch.h
2 files changed, 9 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/19954/1

diff --git a/src/southbridge/intel/bd82x6x/early_usb.c b/src/southbridge/intel/bd82x6x/early_usb.c
index 81d3b6b..faca258 100644
--- a/src/southbridge/intel/bd82x6x/early_usb.c
+++ b/src/southbridge/intel/bd82x6x/early_usb.c
@@ -37,7 +37,9 @@
    pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */ , 0x80); /* Enable ACPI BAR */

/* Unlock registers.  */
-	outw (inw (DEFAULT_PMBASE | 0x003c) | 2, DEFAULT_PMBASE | 0x003c);
+	outw(inw(DEFAULT_PMBASE | UPRWC) | UPRWC_WR_EN,
+	     DEFAULT_PMBASE | UPRWC);
+
    for (i = 0; i < 14; i++)
    	write32 (DEFAULT_RCBABASE + (0x3500 + 4 * i),
    		 currents[portmap[i].current]);
@@ -69,5 +71,6 @@
    pci_write_config32 (PCI_DEV (0, 0x14, 0), 0xe4, 0x00000000);

/* Relock registers.  */
-	outw (0x0000, DEFAULT_PMBASE | 0x003c);
+	outw(inw(DEFAULT_PMBASE | UPRWC) & ~UPRWC_WR_EN,
+	     DEFAULT_PMBASE | UPRWC);
 }
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h
index f8131da..2126277 100644
--- a/src/southbridge/intel/bd82x6x/pch.h
+++ b/src/southbridge/intel/bd82x6x/pch.h
@@ -113,6 +113,10 @@
 #define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
 #endif

+/* PM I/O Space */
+#define UPRWC			0x3c
+# define  UPRWC_WR_EN	 (1 << 1) // USB Per-Port Registers Write Enable
+
 /* PCI Configuration Space (D30:F0): PCI2PCI */
 #define PSTS	0x06
 #define SMLT	0x1b