Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79301?usp=email )
Change subject: vc/intel/fsp/mtl: Add UPDs for Acoustic Noise Mitigation ......................................................................
vc/intel/fsp/mtl: Add UPDs for Acoustic Noise Mitigation
Acoustic noise in PCBs is a common problem and be caused by a variety of factors, including:
Mechanical vibrations, Electromagnetic interference (EMI) and/or Thermal expansion.
This patch adds the UPDs to FSPM header file for mitigating the acoustic noise.
FSPM: 1. AcousticNoiseMitigation 2. FastPkgCRampDisable 3. SlowSlewRate
BUG=b:312405633 TEST=Able to build and boot google/rex.
Change-Id: Iea0bfa2f92bb82e722ffc1a0b2f1e374b32e4ebc Signed-off-by: Subrata Banik subratabanik@google.com --- M src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h 1 file changed, 82 insertions(+), 49 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/79301/1
diff --git a/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h index 7853004..58923f1 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h @@ -1416,7 +1416,18 @@
/** Offset 0x0585 - Reserved **/ - UINT8 Reserved32[145]; + UINT8 Reserved32[142]; + +/** Offset 0x0613 - Acoustic Noise Mitigation feature + Enabling this option will help mitigate acoustic noise on certain SKUs when the + CPU is in deeper C state. <b>0: Disabled</b>; 1: Enabled + $EN_DIS +**/ + UINT8 AcousticNoiseMitigation; + +/** Offset 0x0614 - Reserved +**/ + UINT8 Reserved33[2];
/** Offset 0x0616 - Platform Power Pmax PSYS PMax power, defined in 1/8 Watt increments. <b>0 - Auto</b> Specified in 1/8 @@ -1426,7 +1437,7 @@
/** Offset 0x0618 - Reserved **/ - UINT8 Reserved33[12]; + UINT8 Reserved34[12];
/** Offset 0x0624 - AcLoadline AC Loadline defined in 1/100 mOhms. A value of 100 = 1.00 mOhm, and 1255 = 12.55 @@ -1465,7 +1476,7 @@
/** Offset 0x0660 - Reserved **/ - UINT8 Reserved34[54]; + UINT8 Reserved35[54];
/** Offset 0x0696 - Thermal Design Current enable/disable Thermal Design Current enable/disable; <b>0: Disable</b>; 1: Enable. [0] for IA, @@ -1482,7 +1493,29 @@
/** Offset 0x06B4 - Reserved **/ - UINT8 Reserved35[166]; + UINT8 Reserved36[128]; + +/** Offset 0x0734 - Disable Fast Slew Rate for Deep Package C States for VR domains + This option needs to be configured to reduce acoustic noise during deeper C states. + False: Don't disable Fast ramp during deeper C states; True: Disable Fast ramp + during deeper C state. [0] for IA, [1] for GT, [2] for SA, [3] through [5] are + Reserved. <b>0: False</b>; 1: True + $EN_DIS +**/ + UINT8 FastPkgCRampDisable[6]; + +/** Offset 0x073A - Slew Rate configuration for Deep Package C States for VR domains + Set VR IA/GT/SA Slow Slew Rate for Deep Package C State ramp time; Slow slew rate + equals to Fast divided by number, the number is 2, 4, 8, 16 to slow down the slew + rate to help minimize acoustic noise; divide by 16 is disabled for GT/SA. <b>0: + Fast/2</b>; 1: Fast/4; 2: Fast/8; 3: Fast/16; 0xFF: Ignore the configuration + 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16, 0xFF: Ignore the configuration +**/ + UINT8 SlowSlewRate[6]; + +/** Offset 0x0740 - Reserved +**/ + UINT8 Reserved37[26];
/** Offset 0x075A - VR Fast Vmode ICC Limit support Voltage Regulator Fast Vmode ICC Limit. A value of 400 = 100A. A value of 0 corresponds @@ -1508,7 +1541,7 @@
/** Offset 0x0772 - Reserved **/ - UINT8 Reserved36[146]; + UINT8 Reserved38[146];
/** Offset 0x0804 - BiosGuard Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable @@ -1530,7 +1563,7 @@
/** Offset 0x0807 - Reserved **/ - UINT8 Reserved37; + UINT8 Reserved39;
/** Offset 0x0808 - PrmrrSize Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable @@ -1544,7 +1577,7 @@
/** Offset 0x0810 - Reserved **/ - UINT8 Reserved38[8]; + UINT8 Reserved40[8];
/** Offset 0x0818 - TxtDprMemoryBase Enable/Disable. 0: Disable, define default value of TxtDprMemoryBase , 1: enable @@ -1599,7 +1632,7 @@
/** Offset 0x0849 - Reserved **/ - UINT8 Reserved39[32]; + UINT8 Reserved41[32];
/** Offset 0x0869 - Enable PCH HSIO PCIE Rx Set Ctle Enable PCH PCIe Gen 3 Set CTLE Value. @@ -1786,7 +1819,7 @@
/** Offset 0x0A85 - Reserved **/ - UINT8 Reserved40; + UINT8 Reserved42;
/** Offset 0x0A86 - SMBUS Base Address SMBUS Base Address (IO space). @@ -1806,7 +1839,7 @@
/** Offset 0x0A99 - Reserved **/ - UINT8 Reserved41[16]; + UINT8 Reserved43[16];
/** Offset 0x0AA9 - SOC/IOE ClkReq-to-ClkSrc mapping Number of ClkReq signal assigned to ClkSrc @@ -1815,7 +1848,7 @@
/** Offset 0x0AB9 - Reserved **/ - UINT8 Reserved42[55]; + UINT8 Reserved44[55];
/** Offset 0x0AF0 - Enable PCH PCIE RP Mask Enable/disable PCH PCIE Root Ports. 0: disable, 1: enable. One bit for each port, @@ -1867,7 +1900,7 @@
/** Offset 0x0AFE - Reserved **/ - UINT8 Reserved43[2]; + UINT8 Reserved45[2];
/** Offset 0x0B00 - DMIC<N> ClkA Pin Muxing (N - DMIC number) Determines DMIC<N> ClkA Pin muxing. See GPIO_*_MUXING_DMIC<N>_CLKA_* @@ -1887,7 +1920,7 @@
/** Offset 0x0B11 - Reserved **/ - UINT8 Reserved44[3]; + UINT8 Reserved46[3];
/** Offset 0x0B14 - DMIC<N> Data Pin Muxing Determines DMIC<N> Data Pin muxing. See GPIO_*_MUXING_DMIC<N>_DATA_* @@ -1912,7 +1945,7 @@
/** Offset 0x0B27 - Reserved **/ - UINT8 Reserved45; + UINT8 Reserved47;
/** Offset 0x0B28 - iDisp-Link T-mode iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 2: 4T, 3: 8T, 4: 16T @@ -1928,7 +1961,7 @@
/** Offset 0x0B2A - Reserved **/ - UINT8 Reserved46[6]; + UINT8 Reserved48[6];
/** Offset 0x0B30 - CNVi DDR RFI Mitigation Enable/Disable DDR RFI Mitigation. Default is ENABLE. 0: DISABLE, 1: ENABLE @@ -1938,7 +1971,7 @@
/** Offset 0x0B31 - Reserved **/ - UINT8 Reserved47[11]; + UINT8 Reserved49[11];
/** Offset 0x0B3C - Debug Interfaces Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub, @@ -1960,7 +1993,7 @@
/** Offset 0x0B3F - Reserved **/ - UINT8 Reserved48; + UINT8 Reserved50;
/** Offset 0x0B40 - Serial Io Uart Debug BaudRate Set default BaudRate Supported from 0 - default to 6000000. Recommended values 9600, @@ -1988,7 +2021,7 @@
/** Offset 0x0B47 - Reserved **/ - UINT8 Reserved49; + UINT8 Reserved51;
/** Offset 0x0B48 - Serial Io Uart Debug Mmio Base Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdSerialIoUartMode @@ -2004,7 +2037,7 @@
/** Offset 0x0B4D - Reserved **/ - UINT8 Reserved50; + UINT8 Reserved52;
/** Offset 0x0B4E - Ring PLL voltage offset Core PLL voltage offset. <b>0: No offset</b>. Range 0-15 @@ -2018,7 +2051,7 @@
/** Offset 0x0B50 - Reserved **/ - UINT8 Reserved51; + UINT8 Reserved53;
/** Offset 0x0B51 - Memory Controller PLL voltage offset Core PLL voltage offset. <b>0: No offset</b>. Range 0-15 @@ -2136,7 +2169,7 @@
/** Offset 0x0B64 - Reserved **/ - UINT8 Reserved52; + UINT8 Reserved54;
/** Offset 0x0B65 - Write Timing Centering 1D Enables/Disable Write Timing Centering 1D @@ -2164,7 +2197,7 @@
/** Offset 0x0B69 - Reserved **/ - UINT8 Reserved53[10]; + UINT8 Reserved55[10];
/** Offset 0x0B73 - Read Equalization Training Enables/Disable Read Equalization Training @@ -2174,7 +2207,7 @@
/** Offset 0x0B74 - Reserved **/ - UINT8 Reserved54[2]; + UINT8 Reserved56[2];
/** Offset 0x0B76 - Write Timing Centering 2D Enables/Disable Write Timing Centering 2D @@ -2202,7 +2235,7 @@
/** Offset 0x0B7A - Reserved **/ - UINT8 Reserved55; + UINT8 Reserved57;
/** Offset 0x0B7B - Command Voltage Centering Enables/Disable Command Voltage Centering @@ -2230,7 +2263,7 @@
/** Offset 0x0B7F - Reserved **/ - UINT8 Reserved56; + UINT8 Reserved58;
/** Offset 0x0B80 - DIMM SPD Alias Test Enables/Disable DIMM SPD Alias Test @@ -2282,7 +2315,7 @@
/** Offset 0x0B88 - Reserved **/ - UINT8 Reserved57[2]; + UINT8 Reserved59[2];
/** Offset 0x0B8A - DIMM CA ODT Training Enable/Disable DIMM CA ODT Training @@ -2292,7 +2325,7 @@
/** Offset 0x0B8B - Reserved **/ - UINT8 Reserved58[3]; + UINT8 Reserved60[3];
/** Offset 0x0B8E - Read Vref Decap Training Enable/Disable Read Vref Decap Training @@ -2314,7 +2347,7 @@
/** Offset 0x0B91 - Reserved **/ - UINT8 Reserved59[4]; + UINT8 Reserved61[4];
/** Offset 0x0B95 - Duty Cycle Correction Training Enable/Disable Duty Cycle Correction Training @@ -2324,7 +2357,7 @@
/** Offset 0x0B96 - Reserved **/ - UINT8 Reserved60[17]; + UINT8 Reserved62[17];
/** Offset 0x0BA7 - ECC Support Enables/Disable ECC Support @@ -2358,7 +2391,7 @@
/** Offset 0x0BB3 - Reserved **/ - UINT8 Reserved61; + UINT8 Reserved63;
/** Offset 0x0BB4 - IbeccProtectedRegionBases IBECC Protected Region Bases per IBECC instance @@ -2450,7 +2483,7 @@
/** Offset 0x0BF0 - Reserved **/ - UINT8 Reserved62[4]; + UINT8 Reserved64[4];
/** Offset 0x0BF4 - Select if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP ESelect if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP @@ -2709,7 +2742,7 @@
/** Offset 0x0C2B - Reserved **/ - UINT8 Reserved63[2]; + UINT8 Reserved65[2];
/** Offset 0x0C2D - Rapl Power Floor Ch0 Power budget ,range[255;0],(0= 5.3W Def) @@ -2760,7 +2793,7 @@
/** Offset 0x0C35 - Reserved **/ - UINT8 Reserved64; + UINT8 Reserved66;
/** Offset 0x0C36 - Power Down Mode This option controls command bus tristating during idle periods @@ -2797,7 +2830,7 @@
/** Offset 0x0C3B - Reserved **/ - UINT8 Reserved65[8]; + UINT8 Reserved67[8];
/** Offset 0x0C43 - Ask MRC to clear memory content Ask MRC to clear memory content <b>0: Do not Clear Memory;</b> 1: Clear Memory. @@ -2812,7 +2845,7 @@
/** Offset 0x0C45 - Reserved **/ - UINT8 Reserved66; + UINT8 Reserved68;
/** Offset 0x0C46 - Post Code Output Port This option configures Post Code Output Port @@ -2832,7 +2865,7 @@
/** Offset 0x0C4A - Reserved **/ - UINT8 Reserved67[2]; + UINT8 Reserved69[2];
/** Offset 0x0C4C - BCLK RFI Frequency Bclk RFI Frequency for each SAGV point in Hz units. 98000000Hz = 98MHz <b>0 - No @@ -2875,7 +2908,7 @@
/** Offset 0x0C62 - Reserved **/ - UINT8 Reserved68[11]; + UINT8 Reserved70[11];
/** Offset 0x0C6D - RH pTRR LFSR1 Mask Row Hammer pTRR LFSR1 Mask, 1/2^(value) @@ -2884,7 +2917,7 @@
/** Offset 0x0C6E - Reserved **/ - UINT8 Reserved69; + UINT8 Reserved71;
/** Offset 0x0C6F - Command Pins Mapping BitMask where bits [3:0] are Controller 0 Channel [3:0] and bits [7:4] are Controller @@ -2900,7 +2933,7 @@
/** Offset 0x0C71 - Reserved **/ - UINT8 Reserved70[3]; + UINT8 Reserved72[3];
/** Offset 0x0C74 - LowerBasicMemTestSize Reduce BasicMemoryTest size WA: 0(Default)=Disable, 1=Enable @@ -2910,7 +2943,7 @@
/** Offset 0x0C75 - Reserved **/ - UINT8 Reserved71[20]; + UINT8 Reserved73[20];
/** Offset 0x0C89 - Skip external display device scanning Enable: Do not scan for external display device, Disable (Default): Scan external @@ -2946,7 +2979,7 @@
/** Offset 0x0C8E - Reserved **/ - UINT8 Reserved72[2]; + UINT8 Reserved74[2];
/** Offset 0x0C90 - PMR Size Size of PMR memory buffer. 0x400000 for normal boot and 0x200000 for S3 boot @@ -2960,7 +2993,7 @@
/** Offset 0x0C95 - Reserved **/ - UINT8 Reserved73[143]; + UINT8 Reserved75[143];
/** Offset 0x0D24 - TotalFlashSize Enable/Disable. 0: Disable, define default value of TotalFlashSize , 1: enable @@ -2976,7 +3009,7 @@
/** Offset 0x0D28 - Reserved **/ - UINT8 Reserved74[28]; + UINT8 Reserved76[28];
/** Offset 0x0D44 - Smbus dynamic power gating Disable or Enable Smbus dynamic power gating. @@ -2992,7 +3025,7 @@
/** Offset 0x0D46 - Reserved **/ - UINT8 Reserved75[2]; + UINT8 Reserved77[2];
/** Offset 0x0D48 - SMBUS SPD Write Disable Set/Clear Smbus SPD Write Disable. 0: leave SPD Write Disable bit; 1: set SPD Write @@ -3003,7 +3036,7 @@
/** Offset 0x0D49 - Reserved **/ - UINT8 Reserved76[34]; + UINT8 Reserved78[34];
/** Offset 0x0D6B - HECI Timeouts 0: Disable, 1: Enable (Default) timeout check for HECI @@ -3056,7 +3089,7 @@
/** Offset 0x0D73 - Reserved **/ - UINT8 Reserved77[100]; + UINT8 Reserved79[100];
/** Offset 0x0DD7 - Avx2 Voltage Guardband Scaling Factor AVX2 Voltage Guardband Scale factor applied to AVX2 workloads. Range is 0-200 in @@ -3079,7 +3112,7 @@
/** Offset 0x0DDA - Reserved **/ - UINT8 Reserved78[2]; + UINT8 Reserved80[2];
/** Offset 0x0DDC - SerialIoUartDebugRxPinMux - FSPM Select RX pin muxing for SerialIo UART used for debug @@ -3105,7 +3138,7 @@
/** Offset 0x0DEC - Reserved **/ - UINT8 Reserved79[164]; + UINT8 Reserved81[164];
/** Offset 0x0E90 - TME Exclude Base Address TME Exclude Base Address. @@ -3125,7 +3158,7 @@
/** Offset 0x0EA1 - Reserved **/ - UINT8 Reserved80[7]; + UINT8 Reserved82[7]; } FSP_M_CONFIG;
/** Fsp M UPD Configuration
-
Subrata Banik (Code Review)