[S] Change in coreboot[main]: soc/intel/pantherlake: Bind SoC config VR settings to respective UPD

[Jérémy Compostella (Code Review)]

Attention is currently required from: Kapil Porwal, Paul Menzel, Pranava Y N, Subrata Banik.

Jérémy Compostella has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/85131?usp=email )

Change subject: soc/intel/pantherlake: Bind SoC config VR settings to respective UPD
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Patch Set 6:

(1 comment)

This change is ready for review.

File src/soc/intel/pantherlake/romstage/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/85131/comment/058d75e6_3dea20f7?usp... :
PS6, Line 271: ARRAY_SIZE(config->enable_fast_vmode
> nit: Can we use NUM_VR_DOMAINS macro directly here?

I have a couple of reasons to like doing it like this but the most important is
that it does not bind this code to a declared constant. Instead the compiler provides the size at compilation time avoid any de-synchronization between declaration and use.