[M] Change in coreboot[master]: soc/intel/alderlake: Add IBECC

[Maximilian Brune (Code Review)]

Attention is currently required from: Paul Menzel, Christian Walter, Tim Wawrzynczak, Maximilian Brune, Lean Sheng Tan, David Milosevic.

Hello build bot (Jenkins), Christian Walter, Tim Wawrzynczak, Angel Pons, Lean Sheng Tan, David Milosevic,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/68756

to look at the new patch set (#6).

Change subject: soc/intel/alderlake: Add IBECC
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soc/intel/alderlake: Add IBECC

Add In Band Error Correction Code to Alderlake SOC's.
It's currently needed and tested for the Prodrive Atlas mainboard.
on the Atlas Board. After enabling it in the UPD, FSP-M takes care of
enabling IBECC.

Signed-off-by: Maximilian Brune 
Change-Id: I9cc2ed6defa1223aa422b9b0d8145f8f8b3dd12e
---
M src/soc/intel/alderlake/chip.h
M src/soc/intel/alderlake/romstage/fsp_params.c
2 files changed, 52 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/68756/6