New patch to review for coreboot: soc/intel/apollolake: enable WB cache for cbmem region in romstage

[Andrey Petrov]

Andrey Petrov ([e-mail]) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14095

-gerrit

commit cecad57bcadecf45ae46b73f5ae6dab21aca01fd
Author: Andrey Petrov 
Date:   Sun Mar 13 16:01:55 2016 -0700

soc/intel/apollolake: enable WB cache for cbmem region in romstage

Since ramstage is run in cbmem that is placed in DRAM, it is imporant
    to have that region cached. This patch tries to cache 8MiB right below
    cbmem_top which is a safe bet ramstage is covered.

Change-Id: I3f2f6e82f3b9060c7350ddff754cd3dbcf457671
    Signed-off-by: Andrey Petrov 
---
 src/soc/intel/apollolake/romstage.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c
index 7c8924d..159535c 100644
--- a/src/soc/intel/apollolake/romstage.c
+++ b/src/soc/intel/apollolake/romstage.c
@@ -15,6 +15,7 @@
 #include <arch/symbols.h>
 #include <cbfs.h>
 #include <cbmem.h>
+#include <cpu/x86/mtrr.h>
 #include <console/console.h>
 #include <device/pci_def.h>
 #include <fsp/api.h>
@@ -80,6 +81,7 @@ asmlinkage void car_stage_entry(void)
    void *hob_list_ptr;
    struct range_entry fsp_mem;
    struct range_entry reg_car;
+	uintptr_t top_of_ram;

printk(BIOS_DEBUG, "Starting romstage...\n");

@@ -95,6 +97,14 @@ asmlinkage void car_stage_entry(void)
    	die("FSP memory init failed. Giving up.");
    }

+	/*
+	 * Cache 16 MiB area right below cbmem, so that ramstage will be
+	 * decompressed and ran from cached memory. This assumes address
+	 * is at least 16 MiB aligned.
+	 */
+	top_of_ram = (uintptr_t) cbmem_top();
+	set_var_mtrr(1, top_of_ram - 16 * MiB, 16 * MiB, MTRR_TYPE_WRBACK);
+
    fsp_find_reserved_memory(&fsp_mem, hob_list_ptr);

/* initialize cbmem by adding FSP reserved memory first thing */