Change in coreboot[master]: soc/intel/alderlake: Allow mainboard to configure USB2 Phy power gating

[Angel Pons (Code Review)]

Attention is currently required from: Tim Wawrzynczak, Paul Menzel, Sridhar Siricilla, Kane Chen.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63293 )

Change subject: soc/intel/alderlake: Allow mainboard to configure USB2 Phy power gating
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Patch Set 5: Code-Review+1

(1 comment)

File src/soc/intel/alderlake/chip.h:

https://review.coreboot.org/c/coreboot/+/63293/comment/4b672730_a12f5564 
PS4, Line 572: Default 0. Set this to 1 in order to disable PCH USB2 Phy Power gating.
> I will add the comment in other CL.

I'd prefer if you could mention doc#723158 here as well.