[L] Change in coreboot[master]: util/amdfwtool: Deal with psp position in flash offset directly
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/72939?usp=email )
Change subject: util/amdfwtool: Deal with psp position in flash offset directly ......................................................................
util/amdfwtool: Deal with psp position in flash offset directly
It is based on work by Arthur Heymans, 69852.
Get rid of the confusing "position index" and use the relative flash offset as the Kconfig setting instead.
TEST=binary identical on amd/birman amd/majolica amd/gardenia amd/mayan amd/bilby amd/mandolin amd/chausie amd/pademelon pcengines/apu2 google/skyrim google/guybrush google/zork google/kahlee google/myst (The test should be done with INCLUDE_CONFIG_FILE=n)
Change-Id: I26bde0b7c70efe9f5762109f431329ea7f95b7f2 Signed-off-by: Zheng Bao fishbaozi@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/72939 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Felix Held felix-coreboot@felixheld.de --- M src/mainboard/amd/chausie/Kconfig M src/mainboard/amd/majolica/Kconfig M src/mainboard/amd/mandolin/Kconfig M src/mainboard/google/guybrush/Kconfig M src/mainboard/google/kahlee/Kconfig M src/mainboard/google/skyrim/Kconfig M src/mainboard/google/zork/Kconfig M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/Makefile.inc M src/soc/amd/common/Makefile.inc M src/soc/amd/common/block/include/amdblocks/psp_efs.h M src/soc/amd/common/block/psp/Kconfig M src/soc/amd/glinda/Kconfig M src/soc/amd/glinda/Makefile.inc M src/soc/amd/mendocino/Kconfig M src/soc/amd/mendocino/Makefile.inc M src/soc/amd/phoenix/Kconfig M src/soc/amd/phoenix/Makefile.inc M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/Makefile.inc M src/soc/amd/stoneyridge/Kconfig M src/soc/amd/stoneyridge/Makefile.inc M src/soc/amd/stoneyridge/fch.c 23 files changed, 94 insertions(+), 287 deletions(-)
Approvals: Felix Held: Looks good to me, approved build bot (Jenkins): Verified
diff --git a/src/mainboard/amd/chausie/Kconfig b/src/mainboard/amd/chausie/Kconfig index 052d5d7..86e18f5 100644 --- a/src/mainboard/amd/chausie/Kconfig +++ b/src/mainboard/amd/chausie/Kconfig @@ -15,6 +15,8 @@ select PCIEXP_COMMON_CLOCK select PCIEXP_L1_SUB_STATE select SOC_AMD_COMMON_BLOCK_ESPI_RETAIN_PORT80_EN if !SOC_AMD_COMMON_BLOCK_SIMNOW_BUILD + select AMD_FWM_POSITION_C20000_DEFAULT if CHROMEOS + select AMD_FWM_POSITION_820000_DEFAULT if !CHROMEOS select SOC_AMD_COMMON_BLOCK_SIMNOW_SUPPORTED
config FMDFILE @@ -27,13 +29,6 @@ config MAINBOARD_PART_NUMBER default "CHAUSIE"
-config AMD_FWM_POSITION_INDEX - int - default 3 if CHROMEOS - default 4 - help - TODO: might need to be adapted for better placement of files in cbfs - config CHAUSIE_HAVE_MCHP_FW bool "Have Microchip EC firmware?" default n diff --git a/src/mainboard/amd/majolica/Kconfig b/src/mainboard/amd/majolica/Kconfig index 937d0ba..a167dff 100644 --- a/src/mainboard/amd/majolica/Kconfig +++ b/src/mainboard/amd/majolica/Kconfig @@ -10,6 +10,8 @@ select AMD_SOC_CONSOLE_UART select PSP_INIT_ESPI select MAINBOARD_HAS_CHROMEOS + select AMD_FWM_POSITION_C20000_DEFAULT if CHROMEOS + select AMD_FWM_POSITION_820000_DEFAULT if !CHROMEOS
config FMDFILE default "src/mainboard/amd/majolica/chromeos.fmd" if CHROMEOS @@ -21,13 +23,6 @@ config MAINBOARD_PART_NUMBER default "MAJOLICA"
-config AMD_FWM_POSITION_INDEX - int - default 3 if CHROMEOS - default 4 - help - TODO: might need to be adapted for better placement of files in cbfs - config MAJOLICA_HAVE_MCHP_FW bool "Have Microchip EC firmware?" default n diff --git a/src/mainboard/amd/mandolin/Kconfig b/src/mainboard/amd/mandolin/Kconfig index 50b3e5d..20ff1c6 100644 --- a/src/mainboard/amd/mandolin/Kconfig +++ b/src/mainboard/amd/mandolin/Kconfig @@ -12,6 +12,8 @@ select HAVE_ACPI_RESUME select DRIVERS_UART_ACPI select AMD_SOC_CONSOLE_UART if !AMD_LPC_DEBUG_CARD + select AMD_FWM_POSITION_420000_DEFAULT if BOARD_AMD_MANDOLIN + select AMD_FWM_POSITION_820000_DEFAULT if BOARD_AMD_CEREME
config FMDFILE default "src/mainboard/amd/mandolin/variants/$(CONFIG_VARIANT_DIR)/board.fmd" @@ -67,13 +69,6 @@ bool default y
-config AMD_FWM_POSITION_INDEX - int - default 3 if BOARD_AMD_MANDOLIN - default 4 if BOARD_AMD_CEREME - help - TODO: might need to be adapted for better placement of files in cbfs - config MANDOLIN_HAVE_MCHP_FW bool "Have Microchip EC firmware?" default n diff --git a/src/mainboard/google/guybrush/Kconfig b/src/mainboard/google/guybrush/Kconfig index 8ddd3b1..e66419b 100644 --- a/src/mainboard/google/guybrush/Kconfig +++ b/src/mainboard/google/guybrush/Kconfig @@ -49,6 +49,7 @@ select SOC_AMD_COMMON_BLOCK_PSP_FUSE_SPL select SYSTEM_TYPE_LAPTOP select TPM_GOOGLE_CR50 + select AMD_FWM_POSITION_C20000_DEFAULT
config VBOOT select EC_GOOGLE_CHROMEEC_SWITCHES @@ -81,12 +82,6 @@ default "Nipperkin" if BOARD_GOOGLE_NIPPERKIN default "Dewatt" if BOARD_GOOGLE_DEWATT
-config AMD_FWM_POSITION_INDEX - int - default 3 - help - TODO: might need to be adapted for better placement of files in cbfs - config DRIVER_TPM_I2C_BUS hex default 0x03 diff --git a/src/mainboard/google/kahlee/Kconfig b/src/mainboard/google/kahlee/Kconfig index 92896e9..a4a7742 100644 --- a/src/mainboard/google/kahlee/Kconfig +++ b/src/mainboard/google/kahlee/Kconfig @@ -35,6 +35,7 @@ select HAVE_EM100_SUPPORT select SYSTEM_TYPE_LAPTOP select TPM_GOOGLE_CR50 + select AMD_FWM_POSITION_F20000_DEFAULT
if BOARD_GOOGLE_BASEBOARD_KAHLEE
@@ -104,10 +105,6 @@ config CHROMEOS select LP_DEFCONFIG_OVERRIDE if PAYLOAD_DEPTHCHARGE
-config AMD_FWM_POSITION_INDEX - int - default 1 - config DRIVER_TPM_I2C_BUS hex default 0x01 diff --git a/src/mainboard/google/skyrim/Kconfig b/src/mainboard/google/skyrim/Kconfig index dc681e8..44ecfc4 100644 --- a/src/mainboard/google/skyrim/Kconfig +++ b/src/mainboard/google/skyrim/Kconfig @@ -5,10 +5,6 @@
if BOARD_GOOGLE_BASEBOARD_SKYRIM
-config AMD_FWM_POSITION_INDEX - int - default 3 - config BOARD_SPECIFIC_OPTIONS def_bool y select ACPI_S1_NOT_SUPPORTED @@ -49,6 +45,7 @@ select PCIEXP_CLK_PM select PCIEXP_COMMON_CLOCK select PCIEXP_L1_SUB_STATE + select AMD_FWM_POSITION_C20000_DEFAULT
config DEVICETREE default "variants/baseboard/devicetree.cb" diff --git a/src/mainboard/google/zork/Kconfig b/src/mainboard/google/zork/Kconfig index d01b023..1abefb1 100644 --- a/src/mainboard/google/zork/Kconfig +++ b/src/mainboard/google/zork/Kconfig @@ -51,6 +51,7 @@ select DRIVERS_USB_ACPI select DRIVERS_UART_ACPI select DRIVERS_GENERIC_BAYHUB_LV2 + select AMD_FWM_POSITION_E20000_DEFAULT
config ELOG_BOOT_COUNT_CMOS_OFFSET int @@ -126,10 +127,6 @@ # Use default libpayload config select LP_DEFCONFIG_OVERRIDE if PAYLOAD_DEPTHCHARGE
-config AMD_FWM_POSITION_INDEX - int - default 2 - config DRIVER_TPM_I2C_BUS hex default 0x03 diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 2c6e949..d10d857 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -322,39 +322,6 @@
menu "PSP Configuration Options"
-config AMD_FWM_POSITION_INDEX - int "Firmware Directory Table location (0 to 5)" - range 0 5 - default 0 if BOARD_ROMSIZE_KB_512 - default 1 if BOARD_ROMSIZE_KB_1024 - default 2 if BOARD_ROMSIZE_KB_2048 - default 3 if BOARD_ROMSIZE_KB_4096 - default 4 if BOARD_ROMSIZE_KB_8192 - default 5 if BOARD_ROMSIZE_KB_16384 - help - Typically this is calculated by the ROM size, but there may - be situations where you want to put the firmware directory - table in a different location. - 0: 512 KB - 0xFFFA0000 - 1: 1 MB - 0xFFF20000 - 2: 2 MB - 0xFFE20000 - 3: 4 MB - 0xFFC20000 - 4: 8 MB - 0xFF820000 - 5: 16 MB - 0xFF020000 - -comment "AMD Firmware Directory Table set to location for 512KB ROM" - depends on AMD_FWM_POSITION_INDEX = 0 -comment "AMD Firmware Directory Table set to location for 1MB ROM" - depends on AMD_FWM_POSITION_INDEX = 1 -comment "AMD Firmware Directory Table set to location for 2MB ROM" - depends on AMD_FWM_POSITION_INDEX = 2 -comment "AMD Firmware Directory Table set to location for 4MB ROM" - depends on AMD_FWM_POSITION_INDEX = 3 -comment "AMD Firmware Directory Table set to location for 8MB ROM" - depends on AMD_FWM_POSITION_INDEX = 4 -comment "AMD Firmware Directory Table set to location for 16MB ROM" - depends on AMD_FWM_POSITION_INDEX = 5 - config AMDFW_CONFIG_FILE string default "src/soc/amd/cezanne/fw.cfg" diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index 70170ef..7b6c998 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -40,21 +40,12 @@ CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/common
# ROMSIG Normally At ROMBASE + 0x20000 -# Overridden by CONFIG_AMD_FWM_POSITION_INDEX # +-----------+---------------+----------------+------------+ # |0x55AA55AA | | | | # +-----------+---------------+----------------+------------+ # | | PSPDIR ADDR | BIOSDIR ADDR | # +-----------+---------------+----------------+
-$(if $(CONFIG_AMD_FWM_POSITION_INDEX), ,\ - $(error Invalid AMD firmware position index. Check if the board sets a valid ROM size)) - -CEZANNE_FWM_POSITION=$(call int-add, \ - $(call int-subtract, 0xffffffff \ - $(call int-shift-left, \ - 0x80000 $(CONFIG_AMD_FWM_POSITION_INDEX))) 0x20000 1) - # 0x40 accounts for the cbfs_file struct + filename + metadata structs, aligned to 64 bytes # Building the cbfs image will fail if the offset isn't large enough AMD_FW_AB_POSITION := 0x40 @@ -222,7 +213,7 @@ $(OPT_APOB_NV_BASE) \ $(OPT_VERSTAGE_FILE) \ $(OPT_VERSTAGE_SIG_FILE) \ - --location $(call _tohex,$(CEZANNE_FWM_POSITION)) \ + --location $(CONFIG_AMD_FWM_POSITION) \ --multilevel \ --output $@
diff --git a/src/soc/amd/common/Makefile.inc b/src/soc/amd/common/Makefile.inc index c5d952f..e388305 100644 --- a/src/soc/amd/common/Makefile.inc +++ b/src/soc/amd/common/Makefile.inc @@ -47,9 +47,8 @@ add_bootblock = \ $(CBFSTOOL) $(1) add -f $(2) -n apu/amdfw -t amdfw \ -b $(call int-add, \ - $(call int-subtract, 0xffffffff \ - $(call int-shift-left, \ - 0x80000 $(CONFIG_AMD_FWM_POSITION_INDEX))) 0x20000 1) + $(call int-subtract, 0xffffffff $(CONFIG_ROM_SIZE)) 1 $(CONFIG_AMD_FWM_POSITION)) + endif # ifeq ($(CONFIG_RESET_VECTOR_IN_RAM),y)
ifeq ($(CONFIG_VBOOT_GSCVD),y) diff --git a/src/soc/amd/common/block/include/amdblocks/psp_efs.h b/src/soc/amd/common/block/include/amdblocks/psp_efs.h index a930bc9..02f027c 100644 --- a/src/soc/amd/common/block/include/amdblocks/psp_efs.h +++ b/src/soc/amd/common/block/include/amdblocks/psp_efs.h @@ -6,7 +6,7 @@
#include <types.h>
-#define EFS_OFFSET (CONFIG_ROM_SIZE - (0x80000 << CONFIG_AMD_FWM_POSITION_INDEX) + 0x20000) +#define EFS_OFFSET CONFIG_AMD_FWM_POSITION
#define EMBEDDED_FW_SIGNATURE 0x55aa55aa
diff --git a/src/soc/amd/common/block/psp/Kconfig b/src/soc/amd/common/block/psp/Kconfig index d59e6fc..68d6861 100644 --- a/src/soc/amd/common/block/psp/Kconfig +++ b/src/soc/amd/common/block/psp/Kconfig @@ -55,3 +55,71 @@ default n help Select this config to indicate SoC includes Hardware Security Processor(HSP). + +config AMD_FWM_POSITION_20000_DEFAULT + bool "0x20000" + +config AMD_FWM_POSITION_420000_DEFAULT + bool "0x420000" + +config AMD_FWM_POSITION_820000_DEFAULT + bool "0x820000" + +config AMD_FWM_POSITION_C20000_DEFAULT + bool "0xC20000" + +config AMD_FWM_POSITION_E20000_DEFAULT + bool "0xE20000" + +config AMD_FWM_POSITION_F20000_DEFAULT + bool "0xF20000" + +config AMD_FWM_POSITION_FA0000_DEFAULT + bool "0xFA0000" + +choice AMD_FWM_POSITION_CHOICE + prompt "AMD FW position" + default AMD_FWM_POSITION_420000 if AMD_FWM_POSITION_420000_DEFAULT + default AMD_FWM_POSITION_820000 if AMD_FWM_POSITION_820000_DEFAULT + default AMD_FWM_POSITION_C20000 if AMD_FWM_POSITION_C20000_DEFAULT + default AMD_FWM_POSITION_E20000 if AMD_FWM_POSITION_E20000_DEFAULT + default AMD_FWM_POSITION_F20000 if AMD_FWM_POSITION_F20000_DEFAULT + default AMD_FWM_POSITION_FA0000 if AMD_FWM_POSITION_FA0000_DEFAULT + default AMD_FWM_POSITION_20000 + help + Set the position on flash offset where the AMD FW needs to be. + This position is relative to a 16MB flash window. If the flash + size is smaller than 16MB it gets mapped at the top of that window. + +config AMD_FWM_POSITION_20000 + bool "0x20000" + +config AMD_FWM_POSITION_420000 + bool "0x420000" + +config AMD_FWM_POSITION_820000 + bool "0x820000" + +config AMD_FWM_POSITION_C20000 + bool "0xC20000" + +config AMD_FWM_POSITION_E20000 + bool "0xE20000" + +config AMD_FWM_POSITION_F20000 + bool "0xF20000" + +config AMD_FWM_POSITION_FA0000 + bool "0xFA0000" + +endchoice + +config AMD_FWM_POSITION + hex + default 0x20000 if AMD_FWM_POSITION_20000 + default 0x420000 if AMD_FWM_POSITION_420000 + default 0x820000 if AMD_FWM_POSITION_820000 + default 0xc20000 if AMD_FWM_POSITION_C20000 + default 0xe20000 if AMD_FWM_POSITION_E20000 + default 0xf20000 if AMD_FWM_POSITION_F20000 + default 0xfa0000 if AMD_FWM_POSITION_FA0000 diff --git a/src/soc/amd/glinda/Kconfig b/src/soc/amd/glinda/Kconfig index b51cff3..98761a8 100644 --- a/src/soc/amd/glinda/Kconfig +++ b/src/soc/amd/glinda/Kconfig @@ -300,39 +300,6 @@
menu "PSP Configuration Options"
-config AMD_FWM_POSITION_INDEX - int "Firmware Directory Table location (0 to 5)" - range 0 5 - default 0 if BOARD_ROMSIZE_KB_512 - default 1 if BOARD_ROMSIZE_KB_1024 - default 2 if BOARD_ROMSIZE_KB_2048 - default 3 if BOARD_ROMSIZE_KB_4096 - default 4 if BOARD_ROMSIZE_KB_8192 - default 5 if BOARD_ROMSIZE_KB_16384 - help - Typically this is calculated by the ROM size, but there may - be situations where you want to put the firmware directory - table in a different location. - 0: 512 KB - 0xFFFA0000 - 1: 1 MB - 0xFFF20000 - 2: 2 MB - 0xFFE20000 - 3: 4 MB - 0xFFC20000 - 4: 8 MB - 0xFF820000 - 5: 16 MB - 0xFF020000 - -comment "AMD Firmware Directory Table set to location for 512KB ROM" - depends on AMD_FWM_POSITION_INDEX = 0 -comment "AMD Firmware Directory Table set to location for 1MB ROM" - depends on AMD_FWM_POSITION_INDEX = 1 -comment "AMD Firmware Directory Table set to location for 2MB ROM" - depends on AMD_FWM_POSITION_INDEX = 2 -comment "AMD Firmware Directory Table set to location for 4MB ROM" - depends on AMD_FWM_POSITION_INDEX = 3 -comment "AMD Firmware Directory Table set to location for 8MB ROM" - depends on AMD_FWM_POSITION_INDEX = 4 -comment "AMD Firmware Directory Table set to location for 16MB ROM" - depends on AMD_FWM_POSITION_INDEX = 5 - config AMDFW_CONFIG_FILE string "AMD PSP Firmware config file" default "src/soc/amd/glinda/fw.cfg" diff --git a/src/soc/amd/glinda/Makefile.inc b/src/soc/amd/glinda/Makefile.inc index 7d37e6b..e079c4b 100644 --- a/src/soc/amd/glinda/Makefile.inc +++ b/src/soc/amd/glinda/Makefile.inc @@ -44,19 +44,12 @@ CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/common
# ROMSIG Normally At ROMBASE + 0x20000 -# Overridden by CONFIG_AMD_FWM_POSITION_INDEX # +-----------+---------------+----------------+------------+ # |0x55AA55AA | | | | # +-----------+---------------+----------------+------------+ # | | PSPDIR ADDR | BIOSDIR ADDR | # +-----------+---------------+----------------+
-$(if $(CONFIG_AMD_FWM_POSITION_INDEX), ,\ - $(error Invalid AMD firmware position index. Check if the board sets a valid ROM size)) - -# Fixed EFS location -GLINDA_FWM_POSITION=0xff020000 - # 0x40 accounts for the cbfs_file struct + filename + metadata structs, aligned to 64 bytes # Building the cbfs image will fail if the offset isn't large enough AMD_FW_AB_POSITION := 0x40 @@ -240,7 +233,7 @@ $(OPT_VERSTAGE_FILE) \ $(OPT_VERSTAGE_SIG_FILE) \ $(OPT_SPL_TABLE_FILE) \ - --location $(call _tohex,$(GLINDA_FWM_POSITION)) \ + --location $(CONFIG_AMD_FWM_POSITION) \ --output $@
$(PSP_BIOSBIN_FILE): $(PSP_ELF_FILE) $(AMDCOMPRESS) diff --git a/src/soc/amd/mendocino/Kconfig b/src/soc/amd/mendocino/Kconfig index 189c6b9..7497ced 100644 --- a/src/soc/amd/mendocino/Kconfig +++ b/src/soc/amd/mendocino/Kconfig @@ -342,39 +342,6 @@
menu "PSP Configuration Options"
-config AMD_FWM_POSITION_INDEX - int "Firmware Directory Table location (0 to 5)" - range 0 5 - default 0 if BOARD_ROMSIZE_KB_512 - default 1 if BOARD_ROMSIZE_KB_1024 - default 2 if BOARD_ROMSIZE_KB_2048 - default 3 if BOARD_ROMSIZE_KB_4096 - default 4 if BOARD_ROMSIZE_KB_8192 - default 5 if BOARD_ROMSIZE_KB_16384 - help - Typically this is calculated by the ROM size, but there may - be situations where you want to put the firmware directory - table in a different location. - 0: 512 KB - 0xFFFA0000 - 1: 1 MB - 0xFFF20000 - 2: 2 MB - 0xFFE20000 - 3: 4 MB - 0xFFC20000 - 4: 8 MB - 0xFF820000 - 5: 16 MB - 0xFF020000 - -comment "AMD Firmware Directory Table set to location for 512KB ROM" - depends on AMD_FWM_POSITION_INDEX = 0 -comment "AMD Firmware Directory Table set to location for 1MB ROM" - depends on AMD_FWM_POSITION_INDEX = 1 -comment "AMD Firmware Directory Table set to location for 2MB ROM" - depends on AMD_FWM_POSITION_INDEX = 2 -comment "AMD Firmware Directory Table set to location for 4MB ROM" - depends on AMD_FWM_POSITION_INDEX = 3 -comment "AMD Firmware Directory Table set to location for 8MB ROM" - depends on AMD_FWM_POSITION_INDEX = 4 -comment "AMD Firmware Directory Table set to location for 16MB ROM" - depends on AMD_FWM_POSITION_INDEX = 5 - config AMDFW_CONFIG_FILE string "AMD PSP Firmware config file" default "src/soc/amd/mendocino/fw.cfg" diff --git a/src/soc/amd/mendocino/Makefile.inc b/src/soc/amd/mendocino/Makefile.inc index fb58278..41ac61b 100644 --- a/src/soc/amd/mendocino/Makefile.inc +++ b/src/soc/amd/mendocino/Makefile.inc @@ -43,21 +43,12 @@ CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/common
# ROMSIG Normally At ROMBASE + 0x20000 -# Overridden by CONFIG_AMD_FWM_POSITION_INDEX # +-----------+---------------+----------------+------------+ # |0x55AA55AA | | | | # +-----------+---------------+----------------+------------+ # | | PSPDIR ADDR | BIOSDIR ADDR | # +-----------+---------------+----------------+
-$(if $(CONFIG_AMD_FWM_POSITION_INDEX), ,\ - $(error Invalid AMD firmware position index. Check if the board sets a valid ROM size)) - -MENDOCINO_FWM_POSITION=$(call int-add, \ - $(call int-subtract, 0xffffffff \ - $(call int-shift-left, \ - 0x80000 $(CONFIG_AMD_FWM_POSITION_INDEX))) 0x20000 1) - # 0x80 accounts for the cbfs_file struct + filename + metadata structs, aligned to 64 bytes # Building the cbfs image will fail if the offset isn't large enough AMD_FW_AB_POSITION := 0x80 @@ -265,7 +256,7 @@ $(OPT_VERSTAGE_SIG_FILE) \ $(OPT_SPL_TABLE_FILE) \ $(OPT_MANIFEST) \ - --location $(call _tohex,$(MENDOCINO_FWM_POSITION)) \ + --location $(CONFIG_AMD_FWM_POSITION) \ --output $@
ifeq ($(CONFIG_CBFS_VERIFICATION)$(CONFIG_VBOOT_STARTS_IN_BOOTBLOCK),yy) diff --git a/src/soc/amd/phoenix/Kconfig b/src/soc/amd/phoenix/Kconfig index 6bed749..7f6f879 100644 --- a/src/soc/amd/phoenix/Kconfig +++ b/src/soc/amd/phoenix/Kconfig @@ -312,23 +312,6 @@
menu "PSP Configuration Options"
-config AMD_FWM_POSITION_INDEX - int - default 5 - -comment "AMD Firmware Directory Table set to location for 512KB ROM" - depends on AMD_FWM_POSITION_INDEX = 0 -comment "AMD Firmware Directory Table set to location for 1MB ROM" - depends on AMD_FWM_POSITION_INDEX = 1 -comment "AMD Firmware Directory Table set to location for 2MB ROM" - depends on AMD_FWM_POSITION_INDEX = 2 -comment "AMD Firmware Directory Table set to location for 4MB ROM" - depends on AMD_FWM_POSITION_INDEX = 3 -comment "AMD Firmware Directory Table set to location for 8MB ROM" - depends on AMD_FWM_POSITION_INDEX = 4 -comment "AMD Firmware Directory Table set to location for 16MB ROM" - depends on AMD_FWM_POSITION_INDEX = 5 - config AMDFW_CONFIG_FILE string "AMD PSP Firmware config file" default "src/soc/amd/phoenix/fw.cfg" diff --git a/src/soc/amd/phoenix/Makefile.inc b/src/soc/amd/phoenix/Makefile.inc index 852934f..344ece4 100644 --- a/src/soc/amd/phoenix/Makefile.inc +++ b/src/soc/amd/phoenix/Makefile.inc @@ -47,19 +47,12 @@ CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/common
# ROMSIG Normally At ROMBASE + 0x20000 -# Overridden by CONFIG_AMD_FWM_POSITION_INDEX # +-----------+---------------+----------------+------------+ # |0x55AA55AA | | | | # +-----------+---------------+----------------+------------+ # | | PSPDIR ADDR | BIOSDIR ADDR | # +-----------+---------------+----------------+
-$(if $(CONFIG_AMD_FWM_POSITION_INDEX), ,\ - $(error Invalid AMD firmware position index. Check if the board sets a valid ROM size)) - -# Fixed EFS location -PHOENIX_FWM_POSITION=0xff020000 - # 0x40 accounts for the cbfs_file struct + filename + metadata structs, aligned to 64 bytes # Building the cbfs image will fail if the offset isn't large enough AMD_FW_AB_POSITION := 0x40 @@ -269,7 +262,7 @@ $(OPT_VERSTAGE_SIG_FILE) \ $(OPT_SPL_TABLE_FILE) \ $(OPT_MANIFEST) \ - --location $(call _tohex,$(PHOENIX_FWM_POSITION)) \ + --location $(CONFIG_AMD_FWM_POSITION) \ --output $@
ifeq ($(CONFIG_AMDFW_SPLIT),y) diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 9051b43..f4b356c 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -347,39 +347,6 @@
menu "PSP Configuration Options"
-config AMD_FWM_POSITION_INDEX - int "Firmware Directory Table location (0 to 5)" - range 0 5 - default 0 if BOARD_ROMSIZE_KB_512 - default 1 if BOARD_ROMSIZE_KB_1024 - default 2 if BOARD_ROMSIZE_KB_2048 - default 3 if BOARD_ROMSIZE_KB_4096 - default 4 if BOARD_ROMSIZE_KB_8192 - default 5 if BOARD_ROMSIZE_KB_16384 - help - Typically this is calculated by the ROM size, but there may - be situations where you want to put the firmware directory - table in a different location. - 0: 512 KB - 0xFFFA0000 - 1: 1 MB - 0xFFF20000 - 2: 2 MB - 0xFFE20000 - 3: 4 MB - 0xFFC20000 - 4: 8 MB - 0xFF820000 - 5: 16 MB - 0xFF020000 - -comment "AMD Firmware Directory Table set to location for 512KB ROM" - depends on AMD_FWM_POSITION_INDEX = 0 -comment "AMD Firmware Directory Table set to location for 1MB ROM" - depends on AMD_FWM_POSITION_INDEX = 1 -comment "AMD Firmware Directory Table set to location for 2MB ROM" - depends on AMD_FWM_POSITION_INDEX = 2 -comment "AMD Firmware Directory Table set to location for 4MB ROM" - depends on AMD_FWM_POSITION_INDEX = 3 -comment "AMD Firmware Directory Table set to location for 8MB ROM" - depends on AMD_FWM_POSITION_INDEX = 4 -comment "AMD Firmware Directory Table set to location for 16MB ROM" - depends on AMD_FWM_POSITION_INDEX = 5 - config AMDFW_CONFIG_FILE string default "src/soc/amd/picasso/fw.cfg" diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 6a44c6a..4085274 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -46,21 +46,12 @@ CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/common
# ROMSIG Normally At ROMBASE + 0x20000 -# Overridden by CONFIG_AMD_FWM_POSITION_INDEX # +-----------+---------------+----------------+------------+ # |0x55AA55AA | | | | # +-----------+---------------+----------------+------------+ # | | PSPDIR ADDR | BIOSDIR ADDR | # +-----------+---------------+----------------+
-$(if $(CONFIG_AMD_FWM_POSITION_INDEX), ,\ - $(error Invalid AMD firmware position index. Check if the board sets a valid ROM size)) - -PICASSO_FWM_POSITION=$(call int-add, \ - $(call int-subtract, 0xffffffff \ - $(call int-shift-left, \ - 0x80000 $(CONFIG_AMD_FWM_POSITION_INDEX))) 0x20000 1) - # 0x40 accounts for the cbfs_file struct + filename + metadata structs, aligned to 64 bytes # Building the cbfs image will fail if the offset isn't large enough AMD_FW_AB_POSITION := 0x40 @@ -240,7 +231,7 @@ $(OPT_APOB0_NV_BASE) \ $(OPT_VERSTAGE_FILE) \ $(OPT_VERSTAGE_SIG_FILE) \ - --location $(call _tohex,$(PICASSO_FWM_POSITION)) \ + --location $(CONFIG_AMD_FWM_POSITION) \ --output $@
$(PSP_BIOSBIN_FILE): $(PSP_ELF_FILE) $(AMDCOMPRESS) diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index 6091dce..9af7455 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -322,39 +322,6 @@ option to manually attach the generated amdfw.rom outside of cbfs. The location is selected by the FWM position.
-config AMD_FWM_POSITION_INDEX - int "Firmware Directory Table location (0 to 5)" - range 0 5 - default 0 if BOARD_ROMSIZE_KB_512 - default 1 if BOARD_ROMSIZE_KB_1024 - default 2 if BOARD_ROMSIZE_KB_2048 - default 3 if BOARD_ROMSIZE_KB_4096 - default 4 if BOARD_ROMSIZE_KB_8192 - default 5 if BOARD_ROMSIZE_KB_16384 - help - Typically this is calculated by the ROM size, but there may - be situations where you want to put the firmware directory - table in a different location. - 0: 512 KB - 0xFFFA0000 - 1: 1 MB - 0xFFF20000 - 2: 2 MB - 0xFFE20000 - 3: 4 MB - 0xFFC20000 - 4: 8 MB - 0xFF820000 - 5: 16 MB - 0xFF020000 - -comment "AMD Firmware Directory Table set to location for 512KB ROM" - depends on AMD_FWM_POSITION_INDEX = 0 -comment "AMD Firmware Directory Table set to location for 1MB ROM" - depends on AMD_FWM_POSITION_INDEX = 1 -comment "AMD Firmware Directory Table set to location for 2MB ROM" - depends on AMD_FWM_POSITION_INDEX = 2 -comment "AMD Firmware Directory Table set to location for 4MB ROM" - depends on AMD_FWM_POSITION_INDEX = 3 -comment "AMD Firmware Directory Table set to location for 8MB ROM" - depends on AMD_FWM_POSITION_INDEX = 4 -comment "AMD Firmware Directory Table set to location for 16MB ROM" - depends on AMD_FWM_POSITION_INDEX = 5 - config DIMM_SPD_SIZE default 512 # DDR4
diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index 5c0a312..47bdf0f 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -64,7 +64,6 @@ CPPFLAGS_common += -I$(src)/soc/amd/stoneyridge/acpi
# ROMSIG Normally At ROMBASE + 0x20000 -# Overridden by CONFIG_AMD_FWM_POSITION_INDEX # +-----------+---------------+----------------+------------+ # |0x55AA55AA |EC ROM Address |GEC ROM Address |USB3 ROM | # +-----------+---------------+----------------+------------+ @@ -72,11 +71,6 @@ # +-----------+ # # EC ROM should be 64K aligned. -STONEYRIDGE_FWM_POSITION=$(call int-add, \ - $(call int-subtract, 0xffffffff \ - $(call int-shift-left, \ - 0x80000 $(CONFIG_AMD_FWM_POSITION_INDEX))) 0x20000 1) - ### 0
FIRMWARE_LOCATION=$(shell grep -e FIRMWARE_LOCATION $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}') @@ -138,26 +132,24 @@ $(OPT_DEBUG_AMDFWTOOL) \ --config $(CONFIG_AMDFW_CONFIG_FILE) \ --flashsize $(CONFIG_ROM_SIZE) \ - --location $(call _tohex,$(STONEYRIDGE_FWM_POSITION)) \ + --location $(CONFIG_AMD_FWM_POSITION) \ --output $@
ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y)
-# Calculate firmware position inside the ROM -STONEYRIDGE_FWM_ROM_POSITION=$(call int-add, \ - $(call int-subtract, $(CONFIG_ROM_SIZE) \ - $(call int-shift-left, \ - 0x80000 $(CONFIG_AMD_FWM_POSITION_INDEX))) 0x20000) - $(call add_intermediate, add_amdfw, $(obj)/amdfw.rom) printf " DD Adding AMD Firmware at ROM offset 0x%x\n" \ - "$(STONEYRIDGE_FWM_ROM_POSITION)" + "$(CONFIG_AMD_FWM_POSITION)" dd if=$(obj)/amdfw.rom \ of=$< conv=notrunc bs=1 \ - seek=$(STONEYRIDGE_FWM_ROM_POSITION) >/dev/null 2>&1 + seek=$(CONFIG_AMD_FWM_POSITION) >/dev/null 2>&1
else # ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y)
+STONEYRIDGE_FWM_POSITION=$(call int-add, \ + $(call int-subtract, 0xffffffff $(CONFIG_ROM_SIZE)) \ + 1 \ + $(CONFIG_AMD_FWM_POSITION)) cbfs-files-y += apu/amdfw apu/amdfw-file := $(obj)/amdfw.rom apu/amdfw-position := $(STONEYRIDGE_FWM_POSITION) diff --git a/src/soc/amd/stoneyridge/fch.c b/src/soc/amd/stoneyridge/fch.c index 9680fb2..176c263 100644 --- a/src/soc/amd/stoneyridge/fch.c +++ b/src/soc/amd/stoneyridge/fch.c @@ -151,7 +151,7 @@ uintptr_t fwaddr; size_t fwsize;
- amdfw_rom = 0x20000 - (0x80000 << CONFIG_AMD_FWM_POSITION_INDEX); + amdfw_rom = 4ull * GiB - CONFIG_ROM_SIZE + CONFIG_AMD_FWM_POSITION; xhci_fw = read32p(amdfw_rom + XHCI_FW_SIG_OFFSET);
fwaddr = 2 + read16p(xhci_fw + XHCI_FW_ADDR_OFFSET + XHCI_FW_BOOTRAM_SIZE);
-
Felix Held (Code Review)