[S] Change in coreboot[master]: mb/siemens/mc_ehl4: Increase payload size for PCIe root port #2 and #3

[Werner Zeh (Code Review)]

Attention is currently required from: Paul Menzel, Mario Scheithauer.

Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75127 )

Change subject: mb/siemens/mc_ehl4: Increase payload size for PCIe root port #2 and #3
......................................................................

Patch Set 4: Code-Review+2

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/75127/comment/5e9a3f34_6f3a1349 
PS3, Line 14: TEST=Measure data transfer during runtime
> If you have the numbers, I’d be interested how much the speed is increased.

Hi Paul. Telling numbers here is hard because it highly depends on how the Software is using this interface. Theoretically the workload is now twice as large which means that the throughput can reach higher values (more data while the same protocol overhead). But it is up to the software use case to decide how big the data packets will really be. If the software decides to stay with 64 bytes per transfer (because it is a DMA transfer for instance) then you will hardly realize a change.
We, in our application, have seen a positive impact if we increase the workload size (again, overall computing time of a task was slightly reduced and I have no numbers concrete for the PCIe transfer).