Change in coreboot[master]: src/soc/intel/common/itss: Add support to get IRQ configuration for P...

[Karthik Ramasubramanian (Code Review)]

Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34089 )

Change subject: src/soc/intel/common/itss: Add support to get IRQ configuration for PCI devices
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Patch Set 10:

(2 comments)

https://review.coreboot.org/c/coreboot/+/34089/10/src/soc/intel/common/block... 
File src/soc/intel/common/block/itss/Kconfig:

https://review.coreboot.org/c/coreboot/+/34089/10/src/soc/intel/common/block... 
PS10, Line 8: depends on SOC_INTEL_CANNONLAKE_BASE || SOC_INTEL_ICELAKE
Can this be marked as default n and then in SOC_INTEL_CANNONLAKE_BASE and SOC_INTEL_ICELAKE you can select SOC_INTEL_COMMON_ITSS_INTERRUPT_OVERRIDE

That way this config can be enabled for appropriate SoCs without the dependency list growing big.

https://review.coreboot.org/c/coreboot/+/34089/10/src/soc/intel/common/block... 
File src/soc/intel/common/block/itss/irq.c:

https://review.coreboot.org/c/coreboot/+/34089/10/src/soc/intel/common/block... 
PS10, Line 108: *num_entries = index;
Just wondering if the IRQ entries exceeds the source buffer capacity, can this *num_entries hold the total number of IRQ entries including the ones that cannot be accommodated here. Thoughts??