Martin L Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69867 )
Change subject: soc/amd: Define post codes ......................................................................
soc/amd: Define post codes
For the most part, this doesn't change any post codes, simply making the existing post-codes into macros.
picasso/romstage.c did get a couple of post codes removed to match the other files.
The POST_ROMSTAGE and POST_BOOTBLOCK codes are intended to become global at some point, while the POST_AGESA and POST_PSP codes would stay AMD specific.
Change-Id: I007a09b6a3ed3280bac674cd74e298ec5c408ab7 --- M src/soc/amd/cezanne/romstage.c M src/soc/amd/common/block/cpu/car/cache_as_ram.S M src/soc/amd/common/block/cpu/noncar/pre_c.S A src/soc/amd/common/block/include/amdblocks/post_codes.h M src/soc/amd/glinda/romstage.c M src/soc/amd/mendocino/romstage.c M src/soc/amd/morgana/romstage.c M src/soc/amd/picasso/romstage.c M src/soc/amd/stoneyridge/bootblock.c M src/soc/amd/stoneyridge/chip.c M src/soc/amd/stoneyridge/romstage.c 11 files changed, 85 insertions(+), 25 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/69867/1
diff --git a/src/soc/amd/cezanne/romstage.c b/src/soc/amd/cezanne/romstage.c index b843bff..2bf5e23 100644 --- a/src/soc/amd/cezanne/romstage.c +++ b/src/soc/amd/cezanne/romstage.c @@ -4,6 +4,7 @@ #include <amdblocks/acpimmio.h> #include <amdblocks/memmap.h> #include <amdblocks/pmlib.h> +#include <amdblocks/post_codes.h> #include <console/console.h> #include <cpu/cpu.h> #include <fsp/api.h> @@ -12,7 +13,7 @@
void __noreturn romstage_main(void) { - post_code(0x40); + post_code(POST_ROMSTAGE_MAIN);
/* Snapshot chipset state prior to any FSP call */ fill_chipset_state(); diff --git a/src/soc/amd/common/block/cpu/car/cache_as_ram.S b/src/soc/amd/common/block/cpu/car/cache_as_ram.S index 251e23a..b38ce80 100644 --- a/src/soc/amd/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/amd/common/block/cpu/car/cache_as_ram.S @@ -8,6 +8,7 @@ ****************************************************************************** */
+#include <amdblocks/post_codes.h> #include <cpu/x86/post_code.h>
.section .init @@ -27,7 +28,7 @@ .global bootblock_pre_c_entry bootblock_pre_c_entry:
- post_code(0xa0) + post_code(POST_BOOTBLOCK_PRE_C_ENTRY)
AMD_ENABLE_STACK
@@ -41,7 +42,7 @@ pushl %eax /* tsc[31:0] */
before_carstage: - post_code(0xa2) + post_code(POST_BOOTBLOCK_PRE_C_DONE)
call bootblock_c_entry /* Never reached */ diff --git a/src/soc/amd/common/block/cpu/noncar/pre_c.S b/src/soc/amd/common/block/cpu/noncar/pre_c.S index 503de3b..e123c36 100644 --- a/src/soc/amd/common/block/cpu/noncar/pre_c.S +++ b/src/soc/amd/common/block/cpu/noncar/pre_c.S @@ -1,12 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0-only */
+#include <amdblocks/post_codes.h> #include <cpu/x86/post_code.h>
.section .init, "ax", @progbits
.global bootblock_resume_entry bootblock_resume_entry: - post_code(0xb0) + post_code(POST_BOOTBLOCK_RESUME_ENTRY)
/* Get an early timestamp */ rdtsc @@ -23,7 +24,7 @@
.global bootblock_pre_c_entry bootblock_pre_c_entry: - post_code(0xa0) + post_code(POST_BOOTBLOCK_PRE_C_ENTRY)
#if ENV_X86_64 #include <cpu/x86/64bit/entry64.inc> @@ -56,7 +57,7 @@ pushl %eax /* tsc[31:0] */ #endif
- post_code(0xa2) + post_code(POST_BOOTBLOCK_PRE_C_DONE)
call bootblock_c_entry /* Never reached */ diff --git a/src/soc/amd/common/block/include/amdblocks/post_codes.h b/src/soc/amd/common/block/include/amdblocks/post_codes.h new file mode 100644 index 0000000..463f57a --- /dev/null +++ b/src/soc/amd/common/block/include/amdblocks/post_codes.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_BLOCK_POST_CODES_H +#define AMD_BLOCK_POST_CODES_H + +#define POST_AGESA_AMDINITRESET 0x37 +#define POST_AGESA_AMDINITEARLY 0x38 + +#define POST_ROMSTAGE_MAIN 0x40 + +#define POST_AGESA_AMDINITPOST 0x40 +#define POST_AGESA_AMDINITPOST_DONE 0x41 + +#define POST_PSP_NOTIFY_DRAM 0x42 +#define POST_PSP_NOTIFY_DRAM 0x43 + +#define POST_ROMSTAGE_RUN_POSTCAR 0x44 + +#define POST_PSP_LOAD_SMU 0x46 +#define POST_AGESA_AMDINITENV 0x47 +#define POST_AGESA_AMDS3LATERESTORE 0x48 + +#define POST_AGESA_AMDINITRESUME 0x60 +#define POST_AGESA_AMDINITRESUME_DONE 0x61 + +#define POST_BOOTBLOCK_SOC_EARLY_INIT 0x90 + + +#define POST_BOOTBLOCK_RESUME_ENTRY 0xb0 +#define POST_BOOTBLOCK_PRE_C_ENTRY 0xa0 +#define POST_BOOTBLOCK_PRE_C_DONE 0xa2 + +#endif diff --git a/src/soc/amd/glinda/romstage.c b/src/soc/amd/glinda/romstage.c index b843bff..2bf5e23 100644 --- a/src/soc/amd/glinda/romstage.c +++ b/src/soc/amd/glinda/romstage.c @@ -4,6 +4,7 @@ #include <amdblocks/acpimmio.h> #include <amdblocks/memmap.h> #include <amdblocks/pmlib.h> +#include <amdblocks/post_codes.h> #include <console/console.h> #include <cpu/cpu.h> #include <fsp/api.h> @@ -12,7 +13,7 @@
void __noreturn romstage_main(void) { - post_code(0x40); + post_code(POST_ROMSTAGE_MAIN);
/* Snapshot chipset state prior to any FSP call */ fill_chipset_state(); diff --git a/src/soc/amd/mendocino/romstage.c b/src/soc/amd/mendocino/romstage.c index 3548a79..0ca32ba 100644 --- a/src/soc/amd/mendocino/romstage.c +++ b/src/soc/amd/mendocino/romstage.c @@ -6,6 +6,7 @@ #include <amdblocks/acpimmio.h> #include <amdblocks/memmap.h> #include <amdblocks/pmlib.h> +#include <amdblocks/post_codes.h> #include <amdblocks/stb.h> #include <console/console.h> #include <cpu/cpu.h> @@ -15,7 +16,7 @@
void __noreturn romstage_main(void) { - post_code(0x40); + post_code(POST_ROMSTAGE_MAIN);
if (CONFIG(WRITE_STB_BUFFER_TO_CONSOLE)) write_stb_to_console(); diff --git a/src/soc/amd/morgana/romstage.c b/src/soc/amd/morgana/romstage.c index b843bff..2bf5e23 100644 --- a/src/soc/amd/morgana/romstage.c +++ b/src/soc/amd/morgana/romstage.c @@ -4,6 +4,7 @@ #include <amdblocks/acpimmio.h> #include <amdblocks/memmap.h> #include <amdblocks/pmlib.h> +#include <amdblocks/post_codes.h> #include <console/console.h> #include <cpu/cpu.h> #include <fsp/api.h> @@ -12,7 +13,7 @@
void __noreturn romstage_main(void) { - post_code(0x40); + post_code(POST_ROMSTAGE_MAIN);
/* Snapshot chipset state prior to any FSP call */ fill_chipset_state(); diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c index 9958af2..846460d 100644 --- a/src/soc/amd/picasso/romstage.c +++ b/src/soc/amd/picasso/romstage.c @@ -3,6 +3,7 @@ #include <acpi/acpi.h> #include <amdblocks/memmap.h> #include <amdblocks/pmlib.h> +#include <amdblocks/post_codes.h> #include <commonlib/helpers.h> #include <console/console.h> #include <cpu/cpu.h> @@ -13,16 +14,14 @@
void __noreturn romstage_main(void) { - post_code(0x40); + post_code(POST_ROMSTAGE_MAIN);
/* Snapshot chipset state prior to any FSP call. */ fill_chipset_state();
- post_code(0x43); fsp_memory_init(acpi_is_wakeup_s3());
memmap_stash_early_dram_usage();
- post_code(0x44); run_ramstage(); } diff --git a/src/soc/amd/stoneyridge/bootblock.c b/src/soc/amd/stoneyridge/bootblock.c index 0a67d9b..f5451f85 100644 --- a/src/soc/amd/stoneyridge/bootblock.c +++ b/src/soc/amd/stoneyridge/bootblock.c @@ -13,6 +13,7 @@ #include <amdblocks/amd_pci_mmconf.h> #include <amdblocks/biosram.h> #include <amdblocks/iomap.h> +#include <amdblocks/post_codes.h> #include <soc/pci_devs.h> #include <soc/cpu.h> #include <soc/southbridge.h> @@ -77,7 +78,7 @@ void bootblock_soc_early_init(void) { bootblock_fch_early_init(); - post_code(0x90); + post_code(POST_BOOTBLOCK_SOC_EARLY_INIT); }
void bootblock_soc_init(void) diff --git a/src/soc/amd/stoneyridge/chip.c b/src/soc/amd/stoneyridge/chip.c index 1633ecd..0a530fc 100644 --- a/src/soc/amd/stoneyridge/chip.c +++ b/src/soc/amd/stoneyridge/chip.c @@ -15,6 +15,7 @@ #include <amdblocks/agesawrapper.h> #include <amdblocks/agesawrapper_call.h> #include <amdblocks/i2c.h> +#include <amdblocks/post_codes.h>
#include "chip.h"
@@ -115,15 +116,15 @@ static void earliest_ramstage(void *unused) { if (!acpi_is_wakeup_s3()) { - post_code(0x46); + post_code(POST_PSP_LOAD_SMU); if (CONFIG(SOC_AMD_PSP_SELECTABLE_SMU_FW)) psp_load_named_blob(BLOB_SMU_FW2, "smu_fw2");
- post_code(0x47); + post_code(POST_AGESA_AMDINITENV); do_agesawrapper(AMD_INIT_ENV, "amdinitenv"); } else { /* Complete the initial system restoration */ - post_code(0x46); + post_code(POST_AGESA_AMDS3LATERESTORE); do_agesawrapper(AMD_S3LATE_RESTORE, "amds3laterestore"); } } diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index 54fc51e..efa256f 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -5,6 +5,7 @@ #include <amdblocks/agesawrapper_call.h> #include <amdblocks/agesawrapper.h> #include <amdblocks/biosram.h> +#include <amdblocks/post_codes.h> #include <amdblocks/psp.h> #include <arch/romstage.h> #include <cbmem.h> @@ -35,10 +36,10 @@
static void agesa_call(void) { - post_code(0x37); + post_code(POST_AGESA_AMDINITRESET); do_agesawrapper(AMD_INIT_RESET, "amdinitreset");
- post_code(0x38); + post_code(POST_AGESA_AMDINITEARLY); /* APs will not exit amdinitearly */ do_agesawrapper(AMD_INIT_EARLY, "amdinitearly"); } @@ -66,10 +67,10 @@ bsp_agesa_call();
if (!s3_resume) { - post_code(0x40); + post_code(POST_AGESA_AMDINITPOST); do_agesawrapper(AMD_INIT_POST, "amdinitpost");
- post_code(0x41); + post_code(POST_AGESA_AMDINITPOST_DONE); /* * TODO: This is a hack to work around current AGESA behavior. * AGESA needs to change to reflect that coreboot owns @@ -99,16 +100,16 @@ wrmsr(SYSCFG_MSR, sys_cfg); } else { printk(BIOS_INFO, "S3 detected\n"); - post_code(0x60); + post_code(POST_AGESA_AMDINITRESUME); do_agesawrapper(AMD_INIT_RESUME, "amdinitresume");
- post_code(0x61); + post_code(POST_AGESA_AMDINITRESUME_DONE); }
- post_code(0x42); + post_code(POST_PSP_NOTIFY_DRAM); psp_notify_dram();
- post_code(0x43); + post_code(POST_PSP_NOTIFY_DRAM_DONE); if (cbmem_recovery(s3_resume)) printk(BIOS_CRIT, "Failed to recover cbmem\n"); if (romstage_handoff_init(s3_resume)) @@ -117,7 +118,7 @@ if (CONFIG(SMM_TSEG)) smm_list_regions();
- post_code(0x44); + post_code(POST_ROMSTAGE_RUN_POSTCAR); prepare_and_run_postcar(); }
-
Martin L Roth (Code Review)