Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29687 )
Change subject: drivers/intel/fsp1_1/cache_as_ram.inc: Dont include soc/car_setup.S ......................................................................
drivers/intel/fsp1_1/cache_as_ram.inc: Dont include soc/car_setup.S
soc/car_setup.S is included when SKIP_FSP_CAR is enabled, but no chipset/SoC have car_setup.S available. Remove include and post_code() call always solving build errors.
BUG=NA TEST=NA
Change-Id: Iebae2940eb10c9ca9054437be4740c79137bcc61 Signed-off-by: Frans Hendriks fhendriks@eltan.com Reviewed-on: https://review.coreboot.org/c/29687 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Huang Jin huang.jin@intel.com --- M src/drivers/intel/fsp1_1/cache_as_ram.inc 1 file changed, 0 insertions(+), 13 deletions(-)
Approvals: build bot (Jenkins): Verified Huang Jin: Looks good to me, approved
diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.inc b/src/drivers/intel/fsp1_1/cache_as_ram.inc index af6f3a9..934ae67 100644 --- a/src/drivers/intel/fsp1_1/cache_as_ram.inc +++ b/src/drivers/intel/fsp1_1/cache_as_ram.inc @@ -37,19 +37,6 @@ cache_as_ram: post_code(0x20)
-#if IS_ENABLED(CONFIG_SKIP_FSP_CAR) - - /* - * SOC specific setup - * NOTE: This has to preserve the registers - * mm0, mm1 and edi. - */ - #include <soc/car_setup.S> - - post_code(0x28) - -#endif - /* * Find the FSP binary in cbfs. * Make a fake stack that has the return value back to this code.