Change in coreboot[master]: acpigen,soc/amd/cezanne,intel/{common,skl}: rework CPPC table passing

[Angel Pons (Code Review)]

Attention is currently required from: Felix Singer, Jason Glenesk, Raul Rangel, Nico Huber, Furquan Shaikh, Marshall Dawson, Tim Wawrzynczak, Michael Niewöhner, Patrick Rudolph, Felix Held.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58118 )

Change subject: acpigen,soc/amd/cezanne,intel/{common,skl}: rework CPPC table passing
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Patch Set 9:

(4 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/58118/comment/8d469c49_7f5e3d26 
PS9, Line 12: Test: dumped SSDT before and after do not differ.
On which machine?

File src/cpu/intel/common/common_init.c:

https://review.coreboot.org/c/coreboot/+/58118/comment/5924fb85_9c3504d3 
PS9, Line 134: 	*version = CPPC_VERSION_2;
I'd use `CPPC_VERSION_3` here.

Context: The code in soc/intel was changed and the CPPC version now depends on `SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID`. As the Kconfig option is specific to soc/intel, I'd return the highest supported CPPC version here, and lower it in soc/intel according to the Kconfig option.

File src/soc/amd/cezanne/cppc.c:

https://review.coreboot.org/c/coreboot/+/58118/comment/fc810e97_e292df36 
PS9, Line 42: const cppc_entry_t *cpu_get_cppc_table(u32 *version, u32 *size)
Do you need this function to be public? It's not used outside of this file. In fact, I'd get rid of it and call `acpigen_write_CPPC_package()` directly with the right parameters.

File src/soc/intel/common/block/acpi/acpi.c:

https://review.coreboot.org/c/coreboot/+/58118/comment/92ce0517_0b19d49a 
PS9, Line 387: 		acpigen_write_CPPC_package(cppc_table, version, size);
This has changed, now the CPPC version can be 2 or 3 depending on the `SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID` Kconfig option. I would have `cpu_get_cppc_table()` return CPPC_VERSION_3 (the highest supported CPPC version) and change the value to CPPC_VERSION_2 if the `SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID` option is not enabled.

I'm thinking of something like this:

if (core_id == 0) {
    u32 version, size;
    const cppc_entry_t *cppc_table = cpu_get_cppc_table(&version, &size);
    if (!CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID))
    	version = CPPC_VERSION_2;
    acpigen_write_CPPC_package(cppc_table, version, size);
 }