Change in coreboot[master]: WIP: soc/intel/cannonlake: Enable Intel DCI TraceHub

[Philipp Hug (Code Review)]

Philipp Hug has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41826 )

Change subject: WIP: soc/intel/cannonlake: Enable Intel DCI TraceHub
......................................................................

WIP: soc/intel/cannonlake: Enable Intel DCI TraceHub

Set PchTraceHubMode and CpuTraceHubMode if TraceHubMode is set.

To use Intel DCI:
* enable the following PCI devices 14.1 xDCI and 1f.7 Trace Hub
* set the TraceHubMode to 2 in the devicetree for remote debugging
* set CONFIG_SOC_INTEL_CANNONLAKE_DEBUG_CONSENT=3 in KConfig

TODO=Add documentation
TEST=Tested on lemp9, debugging works

Change-Id: I86e2aff3002a8d2a9e4d121cafaef79aa3ee981b
Signed-off-by: Philipp Hug 
---
M src/soc/intel/cannonlake/chip.h
M src/soc/intel/cannonlake/romstage/fsp_params.c
2 files changed, 25 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/41826/1

diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index a30f732..f7f8828 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -335,6 +335,21 @@

enum serirq_mode serirq_mode;

+	/*
+	 * TraceHubMode config
+	 * 0: Disable, 1: Target Debugger Mode, 2: Host Debugger Mode
+	 */
+	uint8_t TraceHubMode;
+
+	/* Debug interface selection */
+	enum {
+		DEBUG_INTERFACE_RAM = (1 << 0),
+		DEBUG_INTERFACE_UART_8250IO = (1 << 1),
+		DEBUG_INTERFACE_USB3 = (1 << 3),
+		DEBUG_INTERFACE_LPSS_SERIAL_IO = (1 << 4),
+		DEBUG_INTERFACE_TRACEHUB = (1 << 5),
+	} debug_interface_flag;
+
    /* GPIO SD card detect pin */
    unsigned int sdcard_cd_gpio;

diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c
index c1afd1e..8a8168b 100644
--- a/src/soc/intel/cannonlake/romstage/fsp_params.c
+++ b/src/soc/intel/cannonlake/romstage/fsp_params.c
@@ -67,8 +67,16 @@
     * BIT0-RAM, BIT1-Legacy Uart BIT3-USB3, BIT4-LPSS Uart, BIT5-TraceHub
     * BIT2 - Not used.
     */
-	m_cfg->PcdDebugInterfaceFlags =
-				CONFIG(DRIVERS_UART_8250IO) ? 0x02 : 0x10;
+	m_cfg->PcdDebugInterfaceFlags = CONFIG(DRIVERS_UART_8250IO) ?
+		DEBUG_INTERFACE_UART_8250IO : DEBUG_INTERFACE_LPSS_SERIAL_IO;
+
+	/* TraceHub configuration */
+	dev = pcidev_path_on_root(PCH_DEVFN_TRACEHUB);
+	if (dev && dev->enabled && config->TraceHubMode) {
+		m_cfg->PcdDebugInterfaceFlags |= DEBUG_INTERFACE_TRACEHUB;
+		m_cfg->PchTraceHubMode = config->TraceHubMode;
+		m_cfg->CpuTraceHubMode = config->TraceHubMode;
+	}

/* Change VmxEnable UPD value according to ENABLE_VMX Kconfig */
    m_cfg->VmxEnable = CONFIG(ENABLE_VMX);

[S] Change in coreboot[master]: WIP: soc/intel/cannonlake: Enable Intel DCI TraceHub

[Stefan Reinauer (Code Review)]

Stefan Reinauer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/41826?usp=email )

Change subject: WIP: soc/intel/cannonlake: Enable Intel DCI TraceHub
......................................................................

Abandoned