[XS] Change in coreboot[main]: soc/intel/xeon_sp/ebg/soc_xhci: Check if BAR is reachable

[Shuo Liu (Code Review)]

Attention is currently required from: Christian Walter, Johnny Lin, Jonathan Zhang, Patrick Rudolph, Tim Chu.

Shuo Liu has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/85809?usp=email )

Change subject: soc/intel/xeon_sp/ebg/soc_xhci: Check if BAR is reachable
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Patch Set 3: Code-Review+2

(1 comment)

File src/soc/intel/xeon_sp/ebg/soc_xhci.c:

https://review.coreboot.org/c/coreboot/+/85809/comment/cbb5ad09_f2e580fb?usp... :
PS3, Line 21:
> PCI resource allocation is done by FSP and it assignes BAR in high MMIO while coreboot defaults to l […]

Acknowledged