Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39764 )
Change subject: soc/intel/{apl,glk}: add options to configure GPU ......................................................................
soc/intel/{apl,glk}: add options to configure GPU
Adds options to select the primary GPU device and configure IGD, which allows to override the appropriate FSP options in the SoC code. These changes do not affect the configuration of the boards with the Apollo Lake and Gemini Lake processors, because if these parameters are not defined in the devicetree, they will be set to the default values.
Change-Id: I6e8013980259aadeb3a1fd504d31062ccb5ef7af Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/soc/intel/apollolake/chip.h M src/soc/intel/apollolake/romstage.c 2 files changed, 46 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/39764/1
diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index c7fa3e7..8bea454 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -48,6 +48,39 @@ /* Common structure containing soc config data required by common code*/ struct soc_intel_common_config common_soc_config;
+ /* Select DVMT 5.0 Pre-Allocated (Fixed) Graphics Memory size */ + enum { + DVMT_64MB = 2, /* Default */ + DVMT_96MB, + DVMT_128MB, + DVMT_160MB, + DVMT_192MB, + DVMT_224MB, + DVMT_256MB, + DVMT_288MB, + DVMT_320MB, + DVMT_352MB, + DVMT_384MB, + DVMT_416MB, + DVMT_448MB, + DVMT_480MB, + DVMT_512MB, + } igd_dvmt_50_pre_alloc_size; + + /* Select the Aperture Size for GPU device */ + enum { + APERTURE_128MB = 1, /* Default */ + APERTURE_256MB, + APERTURE_512MB, + } igd_aperture_size; + + /* Select the GTT Size for GPU device */ + enum { + GTT_2MB = 1, + GTT_4MB, + GTT_8MB, /* Default */ + } igd_gtt_size; + /* * Mapping from PCIe root port to CLKREQ input on the SOC. The SOC has * four CLKREQ inputs, but six root ports. Root ports without an diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 2efb520..5872e7a 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -264,10 +264,23 @@ static void soc_gpu_init_params(FSPM_UPD *mupd) { FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; + const struct soc_intel_apollolake_config *soc_cfg = config_of_soc(); const struct device *dev = pcidev_path_on_root(SA_DEVFN_IGD);
if (dev && dev->enabled && CONFIG(ONBOARD_VGA_IS_PRIMARY) { m_cfg->PrimaryVideoAdaptor = PRIMARY_IGD; + /* + * Override FSP settings for IGD only if they are set in the devicetree. + * Otherwise, the default values from UPD will be used for them + */ + if (soc_cfg->igd_dvmt_50_pre_alloc_size) + m_cfg->IgdDvmt50PreAlloc = soc_cfg->igd_dvmt_50_pre_alloc_size; + + if (soc_cfg->igd_aperture_size) + m_cfg->IgdApertureSize = soc_cfg->igd_aperture_size; + + if (soc_cfg->igd_gtt_size) + m_cfg->GttSize = soc_cfg->igd_gtt_size; } else { m_cfg->PrimaryVideoAdaptor = PRIMARY_PCI; }
Hello build bot (Jenkins), Andrey Petrov, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39764
to look at the new patch set (#2).
Change subject: soc/intel/{apl,glk}: add options to configure GPU ......................................................................
soc/intel/{apl,glk}: add options to configure GPU
Adds options to select the primary GPU device and configure IGD, which allows to override the appropriate FSP options in the SoC code. These changes do not affect the configuration of the boards with the Apollo Lake and Gemini Lake processors, because if these parameters are not defined in the devicetree, they will be set to the default values.
Change-Id: I6e8013980259aadeb3a1fd504d31062ccb5ef7af Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/soc/intel/apollolake/chip.h M src/soc/intel/apollolake/romstage.c 2 files changed, 49 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/39764/2
Hello build bot (Jenkins), Andrey Petrov, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39764
to look at the new patch set (#4).
Change subject: soc/intel/{apl,glk}: add options to configure IGD [FOR TEST] ......................................................................
soc/intel/{apl,glk}: add options to configure IGD [FOR TEST]
Adds options to configure IGD:
* igd_dvmt_50_pre_alloc_size - pre-allocated graphics memory size * igd_aperture_size - aperture size * igd_gtt_size - GTT Size
Allows to override the appropriate FSP options in the SoC code. These changes do not affect the configuration of the boards with the Apollo Lake and Gemini Lake processors, because if these parameters are not defined in the devicetree, they will be set to the default values.
Changing these parameters is necessary when the embedded system (COMe module) is used for video processing.
Change-Id: I6e8013980259aadeb3a1fd504d31062ccb5ef7af Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/soc/intel/apollolake/chip.h M src/soc/intel/apollolake/romstage.c 2 files changed, 47 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/39764/4
Hello build bot (Jenkins), Andrey Petrov, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39764
to look at the new patch set (#5).
Change subject: soc/intel/{apl,glk}: add options to configure IGD [FOR TEST] ......................................................................
soc/intel/{apl,glk}: add options to configure IGD [FOR TEST]
Adds options to configure IGD:
* igd_dvmt_50_pre_alloc_size - pre-allocated graphics memory size * igd_aperture_size - aperture size * igd_gtt_size - GTT Size
Allows to override the appropriate FSP options in the SoC code. These changes do not affect the configuration of the boards with the Apollo Lake and Gemini Lake processors, because if these parameters are not defined in the devicetree, they will be set to the default values.
Changing these parameters is necessary when the embedded system (COMe module) is used for video processing.
Change-Id: I6e8013980259aadeb3a1fd504d31062ccb5ef7af Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/soc/intel/apollolake/chip.h M src/soc/intel/apollolake/romstage.c 2 files changed, 46 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/39764/5
Maxim Polyakov has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/39764 )
Change subject: soc/intel/{apl,glk}: add options to configure IGD [FOR TEST] ......................................................................
Abandoned
-
Maxim Polyakov (Code Review)