Patch merged into coreboot/master: 0f5cf5e PCI IRQs: Swizzle PCI IRQs for PCI bridges

the following patch was just integrated into master:
commit 0f5cf5e45b78d2e6a91d978bb86de5a4ff07c4d5
Author: Mike Loptien <[e-mail]>
Date:   Mon May 12 21:46:31 2014 -0600

    PCI IRQs: Swizzle PCI IRQs for PCI bridges
    
    The PCI Specification states that devices that implement
    a bridge and a secondary bus must swizzle (rotate) the
    interrupt pins according to the table below:
    	Child Dev #     Child PIN       Parent PIN
    	0,4,8,12...     A/B/C/D         A/B/C/D
    	1,5,9,13...     A/B/C/D         B/C/D/A
    	2,6,10,14..     A/B/C/D         C/D/A/B
    	3,7,11,15..     A/B/C/D         D/A/B/C
    
    Which is also described by this equation:
    	PIN_parent = (Pin_child + Dev_child) % 4
    
    When a device is found and its bus number is greater than 0,
    it is on a bridge and needs to be swizzled.  Following the
    string of parents up to the root bus and swizzling as we go
    gives us the desired swizzling result.  When BIOS_SPEW is
    defined, it will print out each step of the swizzling process.
    
    Change-Id: Icafeadd01983282c86e25f560c831c9482c74e68
    Signed-off-by: Martin Roth <[e-mail]>
    Reviewed-on: http://review.coreboot.org/5734
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <[e-mail]>
    Reviewed-by: Mike Loptien <[e-mail]>


See http://review.coreboot.org/5734 for details.

-gerrit