Patch merged into coreboot/master: 433659a fsp_baytrail: Add the FSP version of Intel's Bay Trail-I chip

the following patch was just integrated into master:
commit 433659ad1e864808ec30e90a62ecfd711559c5a9
Author: Martin Roth <[e-mail]>
Date:   Mon May 12 21:55:00 2014 -0600

    fsp_baytrail: Add the FSP version of Intel's Bay Trail-I chip
    
    While similar to the Bay Trail-M/D code based on the MRC, there are
    many differences as well:
    - Obviously, uses the FSP instead of the MRC binaries.
    - FSP does additional hardware setup, so coreboot doesn't need to.
    - Different microcode & microcode loading method
    - Uses the cache_as_ram.inc from the FSP Driver
    - Various other changes in support of the FSP
    Additional changes that don't have to to with the FSP vs MRC:
    - Updated IRQ Routing
    - Different FADT implementation.
    This was validated with FSP:
    BAYTRAIL_FSP_GOLD_002_10-JANUARY-2014.fd
    SHA256: d29eefbb33454bd5314bfaa38fb055d592a757de7b348ed7096cd8c2d65908a5
    MD5: 9360cd915f0d3e4116bbc782233d7b91
    
    Change-Id: Iadadf8cd6cf444ba840e0f76d3aed7825cd7aee4
    Signed-off-by: Martin Roth <[e-mail]>
    Signed-off-by: Martin Roth <[e-mail]>
    Reviewed-on: http://review.coreboot.org/5791
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <[e-mail]>


See http://review.coreboot.org/5791 for details.

-gerrit