David Hendricks has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78786?usp=email )
Change subject: nb/intel/i440bx: Drop self-specific debugging macros ......................................................................
nb/intel/i440bx: Drop self-specific debugging macros
Replace PRINT_DEBUG() macro with printram() from device/dram/common.h for raminit debug messages.
Define a static dummy dump_pci_device() if CONFIG(DEBUG_RAM_SETUP) is disabled. This allows removing the DUMPNORTH() macro.
dump_spd_registers() will be cleaned up separately.
TEST=Timeless binary remains unchanged.
Change-Id: I685a2f1f38c1afab6a08ff9de4bf82c9061aebec Signed-off-by: Keith Hui buurin@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/78786 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Jérémy Compostella jeremy.compostella@intel.com --- M src/northbridge/intel/i440bx/raminit.c 1 file changed, 27 insertions(+), 30 deletions(-)
Approvals: build bot (Jenkins): Verified Jérémy Compostella: Looks good to me, approved
diff --git a/src/northbridge/intel/i440bx/raminit.c b/src/northbridge/intel/i440bx/raminit.c index 54c1b36..f82d54c 100644 --- a/src/northbridge/intel/i440bx/raminit.c +++ b/src/northbridge/intel/i440bx/raminit.c @@ -3,6 +3,7 @@ #include <spd.h> #include <delay.h> #include <stdint.h> +#include <device/dram/common.h> #include <device/mmio.h> #include <device/pci_ops.h> #include <device/pci_def.h> @@ -17,13 +18,9 @@ * Macros and definitions */
-/* Debugging macros. */ -#if CONFIG(DEBUG_RAM_SETUP) -#define PRINT_DEBUG(x...) printk(BIOS_DEBUG, x) -#define DUMPNORTH() dump_pci_device(NB) -#else -#define PRINT_DEBUG(x...) -#define DUMPNORTH() +/* Debugging stub */ +#if !CONFIG(DEBUG_RAM_SETUP) +static void dump_pci_device(unsigned int dev) {} #endif
/* SDRAMC[7:5] - SDRAM Mode Select (SMS). */ @@ -631,7 +628,7 @@ continue; reg = (reg & 0xf8) | refresh_rate_map[(value & 0x7f)];
- PRINT_DEBUG(" Enabling refresh (DRAMC = 0x%02x) for DIMM %02x\n", reg, i); + printram(" Enabling refresh (DRAMC = 0x%02x) for DIMM %02x\n", reg, i); }
pci_write_config8(NB, DRAMC, reg); @@ -645,8 +642,8 @@ { int i, max;
- PRINT_DEBUG("Northbridge %s SDRAM init:\n", "prior to"); - DUMPNORTH(); + printram("Northbridge %s SDRAM init:\n", "prior to"); + dump_pci_device(NB);
max = ARRAY_SIZE(register_values);
@@ -713,12 +710,12 @@ * modules by setting them to a supported size. */ if (sz.side1 > 128) { - PRINT_DEBUG("Side%d was %dMB but only 128MB will be used.\n", + printram("Side%d was %dMB but only 128MB will be used.\n", 1, sz.side1); sz.side1 = 128;
if (sz.side2 > 128) { - PRINT_DEBUG("Side%d was %dMB but only 128MB will be used.\n", + printram("Side%d was %dMB but only 128MB will be used.\n", 2, sz.side2); sz.side2 = 128; } @@ -760,7 +757,7 @@ } else if (value == SPD_MEMORY_TYPE_SDRAM) { sd = 1; } - PRINT_DEBUG("Found DIMM in slot %d\n", i); + printram("Found DIMM in slot %d\n", i);
if (edo && sd) { die_with_post_code(POSTCODE_RAM_FAILURE, @@ -803,12 +800,12 @@ */ value = smbus_read_byte(device, SPD_MODULE_ATTRIBUTES);
- PRINT_DEBUG("DIMM is "); + printram("DIMM is "); if ((value & MODULE_REGISTERED) == 0) { regsd = 0; - PRINT_DEBUG("not "); + printram("not "); } - PRINT_DEBUG("registered\n"); + printram("registered\n");
/* Calculate page size in bits. */ value = ((1 << col) * width); @@ -839,7 +836,7 @@ /* Page sizes larger than supported are * set to 8KB to use module partially. */ - PRINT_DEBUG("Page size forced to 8KB.\n"); + printram("Page size forced to 8KB.\n"); dra = 0x2; /* 8KB */ } else { dra = -1; @@ -859,7 +856,7 @@ dra = 0x0a; /* 8KB */ } else if (dra >= 16) { /* Ditto */ - PRINT_DEBUG("Page size forced to 8KB.\n"); + printram("Page size forced to 8KB.\n"); dra = 0x0a; /* 8KB */ } else { dra = -1; @@ -918,15 +915,15 @@
/* Set paging policy register. */ pci_write_config8(NB, PGPOL + 1, bpr); - PRINT_DEBUG("%s has been set to 0x%02x\n", "PGPOL[BPR]", bpr); + printram("%s has been set to 0x%02x\n", "PGPOL[BPR]", bpr);
/* Set DRAM row page size register. */ pci_write_config16(NB, RPS, rps); - PRINT_DEBUG("RPS has been set to 0x%04x\n", rps); + printram("RPS has been set to 0x%04x\n", rps);
/* ### ECC */ pci_write_config8(NB, NBXCFG + 3, nbxecc); - PRINT_DEBUG("%s has been set to 0x%02x\n", "NBXCFG[31:24]", nbxecc); + printram("%s has been set to 0x%02x\n", "NBXCFG[31:24]", nbxecc);
/* Set DRAMC[4:3] to proper memory type (EDO/SDRAM/Registered SDRAM). */
@@ -942,7 +939,7 @@ value = pci_read_config8(NB, DRAMC) & 0xe7; value |= i; pci_write_config8(NB, DRAMC, value); - PRINT_DEBUG("%s has been set to 0x%02x\n", "DRAMC", value); + printram("%s has been set to 0x%02x\n", "DRAMC", value); }
static void sdram_enable(void) @@ -953,40 +950,40 @@ udelay(200);
/* 1. Apply NOP. Wait 200 clock cycles (200us should do). */ - PRINT_DEBUG("RAM Enable %d: %s\n", 1, "Apply NOP"); + printram("RAM Enable %d: %s\n", 1, "Apply NOP"); do_ram_command(RAM_COMMAND_NOP); udelay(200);
/* 2. Precharge all. Wait tRP. */ - PRINT_DEBUG("RAM Enable %d: %s\n", 2, "Precharge all"); + printram("RAM Enable %d: %s\n", 2, "Precharge all"); do_ram_command(RAM_COMMAND_PRECHARGE); udelay(1);
/* 3. Perform 8 refresh cycles. Wait tRC each time. */ - PRINT_DEBUG("RAM Enable %d: %s\n", 3, "CBR"); + printram("RAM Enable %d: %s\n", 3, "CBR"); for (i = 0; i < 8; i++) { do_ram_command(RAM_COMMAND_CBR); udelay(1); }
/* 4. Mode register set. Wait two memory cycles. */ - PRINT_DEBUG("RAM Enable %d: %s\n", 4, "Mode register set"); + printram("RAM Enable %d: %s\n", 4, "Mode register set"); do_ram_command(RAM_COMMAND_MRS); udelay(2);
/* 5. Normal operation. */ - PRINT_DEBUG("RAM Enable %d: %s\n", 5, "Normal operation"); + printram("RAM Enable %d: %s\n", 5, "Normal operation"); do_ram_command(RAM_COMMAND_NORMAL); udelay(1);
/* 6. Finally enable refresh. */ - PRINT_DEBUG("RAM Enable %d: %s\n", 6, "Enable refresh"); + printram("RAM Enable %d: %s\n", 6, "Enable refresh"); pci_write_config8(NB, PMCR, 0x10); spd_enable_refresh(); udelay(1);
- PRINT_DEBUG("Northbridge %s SDRAM init:\n", "following"); - DUMPNORTH(); + printram("Northbridge %s SDRAM init:\n", "following"); + dump_pci_device(NB); }
/* Implemented under mainboard. */
-
David Hendricks (Code Review)