Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50274 )
Change subject: intel: Drop FSP_PEIM_TO_PEIM_INTERFACE ......................................................................
intel: Drop FSP_PEIM_TO_PEIM_INTERFACE
This change drops the config FSP_PEIM_TO_PEIM_INTERFACE.
FSP_PEIM_TO_PEIM_INTERFACE is used for: * Auto-selecting FSP_USES_MP_SERVICES_PPI * Including src/drivers/intel/fsp2_0/ppi/Kconfig * Adding ppi to subdirs-y * Setting USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI to y
and is selected by SoCs that want to enable MP PPI services.
Instead of using the indirect path of selecting MP PPI services, this change allows SoC to select FSP_USES_MP_SERVICES_PPI directly. The above uses are handled as follows:
* Auto-selecting FSP_USES_MP_SERVICES_PPI --> This is handled by SoC selection of FSP_USES_MP_SERVICES_PPI. * Including src/drivers/intel/fsp2_0/ppi/Kconfig --> The guard isn't really required. The Kconfig options in this file don't present user prompts and don't really need to be guarded. * Adding ppi to subdirs-y --> Makefile under ppi/ already has conditional inclusion of files and does not require a top-level conditional. * Setting USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI to y --> This is set to y if FSP_USES_MP_SERVICES_PPI is selected by SoC.
TEST=Verified that timeless build for brya, volteer, icelake_rvp, elkhartlake_crb and waddledee shows no change in generated coreboot.rom
Change-Id: I0664f09d85f5be372d19925d47034c76aeeef2ae Signed-off-by: Furquan Shaikh furquan@google.com --- M src/drivers/intel/fsp2_0/Kconfig M src/drivers/intel/fsp2_0/Makefile.inc M src/soc/intel/alderlake/Kconfig M src/soc/intel/common/block/cpu/Kconfig M src/soc/intel/elkhartlake/Kconfig M src/soc/intel/icelake/Kconfig M src/soc/intel/jasperlake/Kconfig M src/soc/intel/tigerlake/Kconfig 8 files changed, 7 insertions(+), 21 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/50274/1
diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 14d9742..0d25630 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -173,16 +173,6 @@ This allows deployed systems to bump their version number with the same FSP which will trigger a retrain of the memory.
-config FSP_PEIM_TO_PEIM_INTERFACE - bool - select FSP_USES_MP_SERVICES_PPI - help - This option allows SOC user to create specific PPI for Intel FSP - usage, coreboot will provide required PPI structure definitions - along with all APIs as per EFI specification. So far this feature - is limited till EFI_PEI_MP_SERVICE_PPI and this option might be - useful to add further PPI if required. - config HAVE_FSP_LOGO_SUPPORT bool default n @@ -272,8 +262,6 @@ will use the FSP EAS v2.0 section 12.2.2 (OEM Status Code) to indicate that a reset is required.
-if FSP_PEIM_TO_PEIM_INTERFACE source "src/drivers/intel/fsp2_0/ppi/Kconfig" -endif
endif diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index b518bec..0943080 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -95,7 +95,6 @@ CPPFLAGS_common+=-I$(CONFIG_FSP_HEADER_PATH) endif
-# Include PPI directory of CONFIG_FSP_PEIM_TO_PEIM_INTERFACE is enable -subdirs-$(CONFIG_FSP_PEIM_TO_PEIM_INTERFACE) += ppi +subdirs-y += ppi
endif diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 806c91b..0474750 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -39,7 +39,7 @@ select PARALLEL_MP_AP_WORK select MICROCODE_BLOB_UNDISCLOSED select PLATFORM_USES_FSP2_2 - select FSP_PEIM_TO_PEIM_INTERFACE + select FSP_USES_MP_SERVICES_PPI select REG_SCRIPT select PMC_GLOBAL_RESET_ENABLE_LOCK select PMC_LOW_POWER_MODE_PROGRAM diff --git a/src/soc/intel/common/block/cpu/Kconfig b/src/soc/intel/common/block/cpu/Kconfig index 2b630d0..f4249c6 100644 --- a/src/soc/intel/common/block/cpu/Kconfig +++ b/src/soc/intel/common/block/cpu/Kconfig @@ -75,8 +75,7 @@
config USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI bool "Perform MP Initialization by FSP using coreboot MP PPI service" - depends on FSP_USES_MP_SERVICES_PPI - default y if FSP_PEIM_TO_PEIM_INTERFACE + default y if FSP_USES_MP_SERVICES_PPI default n help This option allows FSP to make use of MP services PPI published by diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig index 7ad103d..3492640 100644 --- a/src/soc/intel/elkhartlake/Kconfig +++ b/src/soc/intel/elkhartlake/Kconfig @@ -31,7 +31,7 @@ select PARALLEL_MP_AP_WORK select MICROCODE_BLOB_UNDISCLOSED select PLATFORM_USES_FSP2_1 - select FSP_PEIM_TO_PEIM_INTERFACE + select FSP_USES_MP_SERVICES_PPI select REG_SCRIPT select PMC_GLOBAL_RESET_ENABLE_LOCK select PMC_LOW_POWER_MODE_PROGRAM diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index a14be36..dc62b10 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -31,7 +31,7 @@ select PARALLEL_MP_AP_WORK select MICROCODE_BLOB_UNDISCLOSED select PLATFORM_USES_FSP2_1 - select FSP_PEIM_TO_PEIM_INTERFACE + select FSP_USES_MP_SERVICES_PPI select REG_SCRIPT select PMC_GLOBAL_RESET_ENABLE_LOCK select PMC_LOW_POWER_MODE_PROGRAM diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index 5324d84..633a19c 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -32,7 +32,7 @@ select PARALLEL_MP_AP_WORK select MICROCODE_BLOB_UNDISCLOSED select PLATFORM_USES_FSP2_2 - select FSP_PEIM_TO_PEIM_INTERFACE + select FSP_USES_MP_SERVICES_PPI select REG_SCRIPT select PMC_GLOBAL_RESET_ENABLE_LOCK select PMC_LOW_POWER_MODE_PROGRAM diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index cd84bdf..16efca8 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -35,7 +35,7 @@ select PARALLEL_MP_AP_WORK select MICROCODE_BLOB_UNDISCLOSED select PLATFORM_USES_FSP2_2 - select FSP_PEIM_TO_PEIM_INTERFACE + select FSP_USES_MP_SERVICES_PPI select REG_SCRIPT select PMC_GLOBAL_RESET_ENABLE_LOCK select PMC_LOW_POWER_MODE_PROGRAM
-
Furquan Shaikh (Code Review)