Hello Michał Żygowski,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/37349
to review the following change.
Change subject: AGESA,binaryPI: Remove redundant SSE enable ......................................................................
AGESA,binaryPI: Remove redundant SSE enable
Change-Id: Ib3bf731b74cb20e886d3ecd483b37b1e3fc64ebf Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/drivers/amd/agesa/cache_as_ram.S 1 file changed, 0 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/37349/1
diff --git a/src/drivers/amd/agesa/cache_as_ram.S b/src/drivers/amd/agesa/cache_as_ram.S index e3e5735..e429bba 100644 --- a/src/drivers/amd/agesa/cache_as_ram.S +++ b/src/drivers/amd/agesa/cache_as_ram.S @@ -22,7 +22,6 @@ */
#include "gcccar.inc" -#include <cpu/x86/cache.h> #include <cpu/x86/post_code.h>
.code32 @@ -35,15 +34,6 @@
post_code(0xa0)
- /* enable SSE2 128bit instructions */ - /* Turn on OSFXSR [BIT9] and OSXMMEXCPT [BIT10] onto CR4 register */ - - movl %cr4, %eax - orl $(3 << 9), %eax - movl %eax, %cr4 - - post_code(0xa1) - AMD_ENABLE_STACK
/* Align the stack. */
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37349 )
Change subject: AGESA,binaryPI: Remove redundant SSE enable ......................................................................
Patch Set 1: Code-Review+2
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37349 )
Change subject: AGESA,binaryPI: Remove redundant SSE enable ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/37349/1/src/drivers/amd/agesa/cache... File src/drivers/amd/agesa/cache_as_ram.S:
https://review.coreboot.org/c/coreboot/+/37349/1/src/drivers/amd/agesa/cache... PS1, Line 39: /* Turn on OSFXSR [BIT9] and OSXMMEXCPT [BIT10] onto CR4 register */ We need to double-check what the alternative does. And see if romcc bootblock still has this somewhere.
Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37349 )
Change subject: AGESA,binaryPI: Remove redundant SSE enable ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/37349/1/src/drivers/amd/agesa/cache... File src/drivers/amd/agesa/cache_as_ram.S:
https://review.coreboot.org/c/coreboot/+/37349/1/src/drivers/amd/agesa/cache... PS1, Line 39: /* Turn on OSFXSR [BIT9] and OSXMMEXCPT [BIT10] onto CR4 register */
We need to double-check what the alternative does. […]
See arch/x86/bootblock_romcc.S If CONFIG_SSE is selected, SSE is enabled with drivers/cpu/x86/sse_enable.inc The difference here is that the exceptions are not enabled (bit 10).
Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37349 )
Change subject: AGESA,binaryPI: Remove redundant SSE enable ......................................................................
Patch Set 1: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/37349/1/src/drivers/amd/agesa/cache... File src/drivers/amd/agesa/cache_as_ram.S:
https://review.coreboot.org/c/coreboot/+/37349/1/src/drivers/amd/agesa/cache... PS1, Line 39: /* Turn on OSFXSR [BIT9] and OSXMMEXCPT [BIT10] onto CR4 register */
See arch/x86/bootblock_romcc.S […]
Ack
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37349 )
Change subject: AGESA,binaryPI: Remove redundant SSE enable ......................................................................
Patch Set 2: Code-Review+2
Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/37349 )
Change subject: AGESA,binaryPI: Remove redundant SSE enable ......................................................................
AGESA,binaryPI: Remove redundant SSE enable
Change-Id: Ib3bf731b74cb20e886d3ecd483b37b1e3fc64ebf Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/37349 Reviewed-by: Angel Pons th3fanbus@gmail.com Reviewed-by: Arthur Heymans arthur@aheymans.xyz Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/drivers/amd/agesa/cache_as_ram.S 1 file changed, 0 insertions(+), 10 deletions(-)
Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved Angel Pons: Looks good to me, approved Michał Żygowski: Looks good to me, approved
diff --git a/src/drivers/amd/agesa/cache_as_ram.S b/src/drivers/amd/agesa/cache_as_ram.S index e3e5735..e429bba 100644 --- a/src/drivers/amd/agesa/cache_as_ram.S +++ b/src/drivers/amd/agesa/cache_as_ram.S @@ -22,7 +22,6 @@ */
#include "gcccar.inc" -#include <cpu/x86/cache.h> #include <cpu/x86/post_code.h>
.code32 @@ -35,15 +34,6 @@
post_code(0xa0)
- /* enable SSE2 128bit instructions */ - /* Turn on OSFXSR [BIT9] and OSXMMEXCPT [BIT10] onto CR4 register */ - - movl %cr4, %eax - orl $(3 << 9), %eax - movl %eax, %cr4 - - post_code(0xa1) - AMD_ENABLE_STACK
/* Align the stack. */