Change in coreboot[master]: soc/amd/cezanne: Add PCI IRQ Router definitions

[Raul Rangel (Code Review)]

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held.
Hello build bot (Jenkins), Jason Glenesk, Marshall Dawson, Felix Held,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/50451

to look at the new patch set (#2).

Change subject: soc/amd/cezanne: Add PCI IRQ Router definitions
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soc/amd/cezanne: Add PCI IRQ Router definitions

These definitions were identical to picasso. The only thing I changed
was that I renamed Misc1 and Misc2 to HPET_L and HPET_H.

This change still doesn't write the PCI_IRQ register for all the PCI
devices. We need to refactor the picasso pci_gpp code first.

TEST=Boot majolica and see FCH IRQs being programmed.

Signed-off-by: Raul E Rangel 
Change-Id: Ic7e637f234d3af426959a9bbd82a0dcf25bb3c8e
---
M src/soc/amd/cezanne/Kconfig
M src/soc/amd/cezanne/fch.c
A src/soc/amd/cezanne/include/soc/amd_pci_int_defs.h
3 files changed, 69 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/50451/2