Change in coreboot[master]: acpi: Reverse logic for setting PCIEXPWAK_STS bit in PM1_EN_STS

[Nick Vaccaro (Code Review)]

Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/28932

Change subject: acpi: Reverse logic for setting PCIEXPWAK_STS bit in PM1_EN_STS
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acpi: Reverse logic for setting PCIEXPWAK_STS bit in PM1_EN_STS

The logic for setting the PCIEXPWAK_STS is backwards.  According
to EDS, PCIEXPWAK_STS should be set to disable "the inputs to
the PCIEXP_WAKE_STS bit in the PM1 Status register from waking the
system", but the logic was setting that bit if DSX_EN_WAKE_PIN is
enabled, not disabled.  This was causing spurious wake issues on
nocturne.

Changed logic to set the PCIEXPWAK_STS bit if DSX_EN_WAKE_PIN is
not defined in deep_sx_config register in devicetree.cb.

BUG=b:111683988
TEST="emerge-nocturne coreboot chromeos-bootimage', flash build
onto nocturne, boot nocturne, and verify that pulling WAKE# pin
low does not wake the system.

Change-Id: Id8b14ae2ae4d97e184906dec468b405134d590da
Signed-off-by: Nick Vaccaro 
---
M src/soc/intel/skylake/acpi.c
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/28932/1

diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c
index d2ec7e7..bc3ea45 100644
--- a/src/soc/intel/skylake/acpi.c
+++ b/src/soc/intel/skylake/acpi.c
@@ -715,7 +715,7 @@
    	pm1_en |= PWRBTN_STS; /* Always enabled as wake source */
    	if (config->deep_sx_config & DSX_EN_LAN_WAKE_PIN)
    		gpe0_std |= LAN_WAK_EN;
-		if (config->deep_sx_config & DSX_EN_WAKE_PIN)
+		if ((config->deep_sx_config & DSX_EN_WAKE_PIN) == 0)
    		pm1_en |= PCIEXPWAK_STS;
    }