Change in coreboot[master]: soc/intel/common/block/fast_spi: Refactor ROM caching implementation

[Tim Wawrzynczak (Code Review)]

Attention is currently required from: Subrata Banik, Angel Pons, Nick Vaccaro, Kane Chen, Werner Zeh.
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63221 )

Change subject: soc/intel/common/block/fast_spi: Refactor ROM caching implementation
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Patch Set 1: Code-Review+2

(1 comment)

File src/soc/intel/common/block/fast_spi/fast_spi.c:

https://review.coreboot.org/c/coreboot/+/63221/comment/ea451759_6b6417a2 
PS1, Line 203: 	if (mtrr == -1)
is a BIOS_WARNING message valuable here? I guess you can look at the printed MTRRs later, but this might help draw attention if the ROM can't be cached