Change in coreboot[master]: WIP: soc/mediatek/mt8192: print i2c3 timing reg

[Jg Daolongzhu (Code Review)]

Jg Daolongzhu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50366 )

Change subject: WIP: soc/mediatek/mt8192: print i2c3 timing reg
......................................................................

WIP: soc/mediatek/mt8192: print i2c3 timing reg

as title

TEST=Boots correctly on MT8192P1

Signed-off-by: jg_daolongzhu 
Change-Id: Iee6a1e47e7387ecdb7fde999f8bcdaecf03f9f31
---
M src/soc/mediatek/common/i2c.c
1 file changed, 4 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/50366/1

diff --git a/src/soc/mediatek/common/i2c.c b/src/soc/mediatek/common/i2c.c
old mode 100644
new mode 100755
index 3c54b17..7fb883d
--- a/src/soc/mediatek/common/i2c.c
+++ b/src/soc/mediatek/common/i2c.c
@@ -191,6 +191,10 @@

write32(&dma_regs->dma_int_flag, I2C_DMA_CLR_FLAG);
    write32(&dma_regs->dma_en, I2C_DMA_START_EN);
+	printk(BIOS_ERR, "[mtk_debug][i2c%d][addr0x%x] ext_conf(0x%x)\n", bus, addr, read32(&regs->ext_conf));
+printk(BIOS_ERR, "[mtk_debug] timing(0x%x)\n", read32(&regs->timing));
+printk(BIOS_ERR, "[mtk_debug]ltiming(0x%x)\n", read32(&regs->ltiming));
+printk(BIOS_ERR, "[mtk_debug]clock_div(0x%x)\n", read32(&regs->clock_div));

/* start transfer transaction */
    write32(&regs->start, 0x1);