HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38932 )
Change subject: capitalize 'BIOS' ......................................................................
capitalize 'BIOS'
Change-Id: I8303b7baa9671f19a036a59775026ffd63c85273 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M Documentation/ifdtool/layout.md M Documentation/releases/coreboot-4.8.1-relnotes.md M Documentation/soc/intel/apollolake/index.md M Documentation/soc/intel/fit.md M Documentation/tutorial/part1.md M payloads/external/SeaBIOS/Kconfig M src/cpu/x86/smm/smm_module_loader.c M src/device/Kconfig M src/device/oprom/include/x86emu/x86emu.h M src/drivers/intel/gma/int15.c M src/mainboard/asus/p8z77-m_pro/cmos.layout M src/mainboard/asus/p8z77-m_pro/early_init.c M src/mainboard/google/cyan/Kconfig M src/mainboard/google/link/mainboard.c M src/mainboard/google/rambi/mainboard.c M src/mainboard/intel/strago/Kconfig M src/mainboard/kontron/ktqm77/mainboard.c M src/mainboard/lenovo/t420/early_init.c M src/soc/intel/apollolake/chip.c M src/soc/intel/common/block/fast_spi/fast_spi.c M src/soc/intel/common/pch/lockdown/lockdown.c M src/soc/intel/skylake/lockdown.c M util/inteltool/inteltool.8 M util/inteltool/spi.c 24 files changed, 34 insertions(+), 34 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/38932/1
diff --git a/Documentation/ifdtool/layout.md b/Documentation/ifdtool/layout.md index 950db6f..84a9fa7 100644 --- a/Documentation/ifdtool/layout.md +++ b/Documentation/ifdtool/layout.md @@ -42,8 +42,8 @@
```console foo@bar:~$ ifdtool -t bad_image.bin -Region mismatch between bios and SI_BIOS - Descriptor region bios: +Region mismatch between BIOS and SI_BIOS + Descriptor region BIOS: offset: 0x00400000 length: 0x01c00000 FMAP area SI_BIOS: @@ -63,4 +63,4 @@ FMAP area SI_PDR: offset: 0x007fc000 length: 0x00004000 -``` \ No newline at end of file +``` diff --git a/Documentation/releases/coreboot-4.8.1-relnotes.md b/Documentation/releases/coreboot-4.8.1-relnotes.md index 8a6ab96..e246236 100644 --- a/Documentation/releases/coreboot-4.8.1-relnotes.md +++ b/Documentation/releases/coreboot-4.8.1-relnotes.md @@ -40,7 +40,7 @@
Lenovo mainboards ----------------- -* Started integration of VBT (Video Bios Table) binary files to +* Started integration of VBT (Video BIOS Table) binary files to support native graphics initialisation
Internal changes diff --git a/Documentation/soc/intel/apollolake/index.md b/Documentation/soc/intel/apollolake/index.md index d4a5ee5..01f4a7c 100644 --- a/Documentation/soc/intel/apollolake/index.md +++ b/Documentation/soc/intel/apollolake/index.md @@ -5,7 +5,7 @@
With Apollolake Intel invented another flash layout for x86 firmware called IFWI (Intel FirmWare Image).
-Usually on x86 platforms the bootblock is stored at the end of the bios region +Usually on x86 platforms the bootblock is stored at the end of the BIOS region and the Intel ME / TXE has its own IFD region. On Apollolake both have been moved into the IFWI region, which is a subregion of "BIOS", since it allows to store multiple firmware components. diff --git a/Documentation/soc/intel/fit.md b/Documentation/soc/intel/fit.md index 8b638f0..553fef3 100644 --- a/Documentation/soc/intel/fit.md +++ b/Documentation/soc/intel/fit.md @@ -57,4 +57,4 @@ ## References
* [Intel TXT LAB handout](https://downloadmirror.intel.com/18931/eng/Intel%20TXT%20LAB%20Handout.pdf) -* [FIT bios specification](https://www.intel.com/content/dam/www/public/us/en/documents/guides/fit-bios...) +* [FIT BIOS specification](https://www.intel.com/content/dam/www/public/us/en/documents/guides/fit-bios...) diff --git a/Documentation/tutorial/part1.md b/Documentation/tutorial/part1.md index 0c7ef67..159aafe 100644 --- a/Documentation/tutorial/part1.md +++ b/Documentation/tutorial/part1.md @@ -173,7 +173,7 @@ This starts the QEMU emulator with the i440FX host PCI bridge and PIIX3 PCI to ISA bridge. * `-bios build/coreboot.rom` -Use the bios rom image that we just built. If this flag is left out, the +Use the BIOS rom image that we just built. If this flag is left out, the standard SeaBIOS image that comes with QEMU is used. * `-serial stdio` Send the serial output to the console. This allows you to view the coreboot diff --git a/payloads/external/SeaBIOS/Kconfig b/payloads/external/SeaBIOS/Kconfig index 8ec7361..e816775 100644 --- a/payloads/external/SeaBIOS/Kconfig +++ b/payloads/external/SeaBIOS/Kconfig @@ -125,7 +125,7 @@ level 1 - Basic output, interrupts 5, 18h, 19h, 40h, SMP, PNP, PMM level 2 - AHCI, Floppy, Basic ps2, interrupts 11h, 12h, 14h, 17h level 3 - bootsplash, initializations, SeaBIOS VGA BIOS interrupts - level 4 - bios tables, more optionrom + level 4 - BIOS tables, more optionrom level 5 - Extra bootsplash, more XHCI level 6 - ATA commands, extra optionrom level 7 - extra ps2 commands, more OHCI & EHCI diff --git a/src/cpu/x86/smm/smm_module_loader.c b/src/cpu/x86/smm/smm_module_loader.c index 81020a4..a6714b2 100644 --- a/src/cpu/x86/smm/smm_module_loader.c +++ b/src/cpu/x86/smm/smm_module_loader.c @@ -397,7 +397,7 @@ total_size = total_stack_size + handler_size; total_size += fxsave_size + SMM_DEFAULT_SIZE;
- // account for the bios resource list + // account for the BIOS resource list if (CONFIG(STM)) total_size += CONFIG_BIOS_RESOURCE_LIST_SIZE;
diff --git a/src/device/Kconfig b/src/device/Kconfig index a25bb91..603c7eb 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -721,7 +721,7 @@
config INTEL_GMA_ADD_VBT depends on SOC_INTEL_COMMON || CPU_INTEL_COMMON - bool "Add a Video Bios Table (VBT) binary to CBFS" + bool "Add a Video BIOS Table (VBT) binary to CBFS" default y if INTEL_GMA_HAVE_VBT help Add a VBT data file to CBFS. The VBT describes the integrated diff --git a/src/device/oprom/include/x86emu/x86emu.h b/src/device/oprom/include/x86emu/x86emu.h index 4ae82d9..e7f48e4 100644 --- a/src/device/oprom/include/x86emu/x86emu.h +++ b/src/device/oprom/include/x86emu/x86emu.h @@ -170,7 +170,7 @@ #define DEBUG_SVC_F 0x000020 #define DEBUG_FS_F 0x000080 #define DEBUG_PROC_F 0x000100 -#define DEBUG_SYSINT_F 0x000200 /* bios system interrupts. */ +#define DEBUG_SYSINT_F 0x000200 /* BIOS system interrupts. */ #define DEBUG_TRACECALL_F 0x000400 #define DEBUG_INSTRUMENT_F 0x000800 #define DEBUG_MEM_TRACE_F 0x001000 diff --git a/src/drivers/intel/gma/int15.c b/src/drivers/intel/gma/int15.c index 7e0ece3..11efe8c 100644 --- a/src/drivers/intel/gma/int15.c +++ b/src/drivers/intel/gma/int15.c @@ -33,7 +33,7 @@ * bit 2 = Graphics Stretching * bit 1 = Text Stretching * bit 0 = Centering (do not set with bit1 or bit2) - * 0 = video bios default + * 0 = video BIOS default */ X86_AX = 0x005f; X86_CX = pfit; diff --git a/src/mainboard/asus/p8z77-m_pro/cmos.layout b/src/mainboard/asus/p8z77-m_pro/cmos.layout index da29d1c..4ac7b5d 100644 --- a/src/mainboard/asus/p8z77-m_pro/cmos.layout +++ b/src/mainboard/asus/p8z77-m_pro/cmos.layout @@ -77,7 +77,7 @@ 421 2 e 8 usb3_mode
# usb3_drv -# Load (or not) pre-OS xHCI USB3 bios driver +# Load (or not) pre-OS xHCI USB3 BIOS driver # 423 1 e 1 usb3_drv
diff --git a/src/mainboard/asus/p8z77-m_pro/early_init.c b/src/mainboard/asus/p8z77-m_pro/early_init.c index 800d975..6c76a7a 100644 --- a/src/mainboard/asus/p8z77-m_pro/early_init.c +++ b/src/mainboard/asus/p8z77-m_pro/early_init.c @@ -115,7 +115,7 @@ .tseg_size = CONFIG_SMM_TSEG_SIZE, .spd_addresses = { 0xa0, 0xa2, 0xa4, 0xa6 }, /* SMBus mul 2 */ .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, - .ec_present = 0, /* Asus 2203 bios shows XUECA016, but no EC */ + .ec_present = 0, /* Asus 2203 BIOS shows XUECA016, but no EC */ .gbe_enable = 0, /* Board uses no Intel GbE but a RTL8111F */ .dimm_channel0_disabled = 0, /* Both DIMM enabled */ .dimm_channel1_disabled = 0, /* Both DIMM enabled */ diff --git a/src/mainboard/google/cyan/Kconfig b/src/mainboard/google/cyan/Kconfig index 6331419..94ffbc0 100644 --- a/src/mainboard/google/cyan/Kconfig +++ b/src/mainboard/google/cyan/Kconfig @@ -78,7 +78,7 @@ depends on VGA_BIOS default "3rdparty/blobs/mainboard/intel/strago/vgabios.bin" help - The C0 version of the video bios gets computed from this name + The C0 version of the video BIOS gets computed from this name so that they can both be added. Only the correct one for the system will be run.
@@ -87,7 +87,7 @@ depends on VGA_BIOS default "8086,22b0" help - The VGA_BIOS_ID for the C0 version of the video bios is hardcoded + The VGA_BIOS_ID for the C0 version of the video BIOS is hardcoded in soc/intel/braswell/Makefile.inc as 8086,22b1
config CBFS_SIZE diff --git a/src/mainboard/google/link/mainboard.c b/src/mainboard/google/link/mainboard.c index 8be4012..32e5487 100644 --- a/src/mainboard/google/link/mainboard.c +++ b/src/mainboard/google/link/mainboard.c @@ -47,10 +47,10 @@ * bit 2 = Graphics Stretching * bit 1 = Text Stretching * bit 0 = Centering (do not set with bit1 or bit2) - * 0 = video bios default + * 0 = video BIOS default */ X86_AX = 0x005f; - X86_CL = 0x00; /* Use video bios default */ + X86_CL = 0x00; /* Use video BIOS default */ res = 1; break; case 0x5f35: @@ -66,7 +66,7 @@ * bit 7 = LFP2 */ X86_AX = 0x005f; - X86_CX = 0x0000; /* Use video bios default */ + X86_CX = 0x0000; /* Use video BIOS default */ res = 1; break; case 0x5f51: diff --git a/src/mainboard/google/rambi/mainboard.c b/src/mainboard/google/rambi/mainboard.c index d4e38d0..7e9b343 100644 --- a/src/mainboard/google/rambi/mainboard.c +++ b/src/mainboard/google/rambi/mainboard.c @@ -48,7 +48,7 @@ * bit 2 = Graphics Stretching * bit 1 = Text Stretching * bit 0 = Centering (do not set with bit1 or bit2) - * 0 = video bios default + * 0 = video BIOS default */ X86_AX = 0x005f; X86_CX = 0x0001; diff --git a/src/mainboard/intel/strago/Kconfig b/src/mainboard/intel/strago/Kconfig index 5e710a5..640f5d4 100644 --- a/src/mainboard/intel/strago/Kconfig +++ b/src/mainboard/intel/strago/Kconfig @@ -35,7 +35,7 @@ depends on VGA_BIOS default "3rdparty/blobs/mainboard/intel/strago/vgabios.bin" help - The C0 version of the video bios gets computed from this name + The C0 version of the video BIOS gets computed from this name so that they can both be added. Only the correct one for the system will be run.
@@ -44,7 +44,7 @@ depends on VGA_BIOS default "8086,22b0" help - The VGA_BIOS_ID for the C0 version of the video bios is hardcoded + The VGA_BIOS_ID for the C0 version of the video BIOS is hardcoded in soc/intel/braswell/Makefile.inc as 8086,22b1
config EC_GOOGLE_CHROMEEC_BOARDNAME diff --git a/src/mainboard/kontron/ktqm77/mainboard.c b/src/mainboard/kontron/ktqm77/mainboard.c index 2af5eb2..5cd3fc4 100644 --- a/src/mainboard/kontron/ktqm77/mainboard.c +++ b/src/mainboard/kontron/ktqm77/mainboard.c @@ -41,12 +41,12 @@ * bit 2 = Graphics Stretching * bit 1 = Text Stretching * bit 0 = Centering (do not set with bit1 or bit2) - * 0 = video bios default + * 0 = video BIOS default */ X86_EAX &= 0xffff0000; X86_EAX |= 0x005f; X86_ECX &= 0xffffff00; - X86_ECX |= 0x00; /* Use video bios default */ + X86_ECX |= 0x00; /* Use video BIOS default */ res = 1; break; case 0x5f35: @@ -64,7 +64,7 @@ X86_EAX &= 0xffff0000; X86_EAX |= 0x005f; X86_ECX &= 0xffff0000; - X86_ECX |= 0x0000; /* Use video bios default */ + X86_ECX |= 0x0000; /* Use video BIOS default */ res = 1; break; case 0x5f51: diff --git a/src/mainboard/lenovo/t420/early_init.c b/src/mainboard/lenovo/t420/early_init.c index 2e39885..c675512 100644 --- a/src/mainboard/lenovo/t420/early_init.c +++ b/src/mainboard/lenovo/t420/early_init.c @@ -48,7 +48,7 @@ pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32); }
-// OC3 set in bios to port 2-7, OC7 set in bios to port 10-13 +// OC3 set in BIOS to port 2-7, OC7 set in BIOS to port 10-13 const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 1, 0 }, /* P0: system port 4, OC0 */ { 1, 1, 1 }, /* P1: system port 2 (EHCI debug), OC 1 */ diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index d9c42f9..b9c5a4f 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -733,7 +733,7 @@ /* Enable Audio clk gate and power gate */ silconfig->HDAudioClkGate = cfg->hdaudio_clk_gate_enable; silconfig->HDAudioPwrGate = cfg->hdaudio_pwr_gate_enable; - /* Bios config lockdown Audio clk and power gate */ + /* BIOS config lockdown Audio clk and power gate */ silconfig->BiosCfgLockDown = cfg->hdaudio_bios_config_lockdown; if (CONFIG(SOC_INTEL_GLK)) glk_fsp_silicon_init_params_cb(cfg, silconfig); diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c index 019976a..49284e9 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi.c @@ -237,7 +237,7 @@
/* LOCAL APIC default address is 0xFEE0000, bios_size over 16MB will * cause memory type conflict when setting memory type to write - * protection, so limit the cached bios region to be no more than 16MB. + * protection, so limit the cached BIOS region to be no more than 16MB. * */ bios_size = MIN(bios_size, 16 * MiB); if (bios_size <= 0) diff --git a/src/soc/intel/common/pch/lockdown/lockdown.c b/src/soc/intel/common/pch/lockdown/lockdown.c index 4a3209e..3fa6e77 100644 --- a/src/soc/intel/common/pch/lockdown/lockdown.c +++ b/src/soc/intel/common/pch/lockdown/lockdown.c @@ -69,12 +69,12 @@ /* Lock FAST_SPIBAR */ fast_spi_lock_bar();
- /* Set Bios Interface Lock, Bios Lock */ + /* Set BIOS Interface Lock, BIOS Lock */ if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) { - /* Bios Interface Lock */ + /* BIOS Interface Lock */ fast_spi_set_bios_interface_lock_down();
- /* Bios Lock */ + /* BIOS Lock */ fast_spi_set_lock_enable(); } } diff --git a/src/soc/intel/skylake/lockdown.c b/src/soc/intel/skylake/lockdown.c index 66dae8c..6911744 100644 --- a/src/soc/intel/skylake/lockdown.c +++ b/src/soc/intel/skylake/lockdown.c @@ -22,7 +22,7 @@
static void lpc_lockdown_config(int chipset_lockdown) { - /* Set Bios Interface Lock, Bios Lock */ + /* Set BIOS Interface Lock, BIOS Lock */ if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) { lpc_set_bios_interface_lock_down(); lpc_set_lock_enable(); diff --git a/util/inteltool/inteltool.8 b/util/inteltool/inteltool.8 index 86a76bd..01e3cfd 100644 --- a/util/inteltool/inteltool.8 +++ b/util/inteltool/inteltool.8 @@ -32,7 +32,7 @@ Dump I/O Controller Hub (ICH) southbridge RCBA registers. .TP .B "-s, --spi" -Dump I/O Controller Hub (ICH) southbridge SPI registers and bios control. +Dump I/O Controller Hub (ICH) southbridge SPI registers and BIOS control. .TP .B "-f, --gfx" .RB "Dump graphics registers. " \ diff --git a/util/inteltool/spi.c b/util/inteltool/spi.c index 22ba3d4..e8289ac 100644 --- a/util/inteltool/spi.c +++ b/util/inteltool/spi.c @@ -22,7 +22,7 @@ { 0x1, 1, "BLE - lock enable" }, { 0x2, 2, "SPI Read configuration" }, { 0x4, 1, "TopSwapStatus" }, - { 0x5, 1, "SMM Bios Write Protect Disable" }, + { 0x5, 1, "SMM BIOS Write Protect Disable" }, { 0x6, 2, "reserved" }, };
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38932 )
Change subject: capitalize 'BIOS' ......................................................................
Patch Set 1: Code-Review+1
(2 comments)
https://review.coreboot.org/c/coreboot/+/38932/1/Documentation/ifdtool/layou... File Documentation/ifdtool/layout.md:
https://review.coreboot.org/c/coreboot/+/38932/1/Documentation/ifdtool/layou... PS1, Line 45: BIOS That's the actual output of the tool.
https://review.coreboot.org/c/coreboot/+/38932/1/Documentation/soc/intel/apo... File Documentation/soc/intel/apollolake/index.md:
https://review.coreboot.org/c/coreboot/+/38932/1/Documentation/soc/intel/apo... PS1, Line 8: bios That's a name
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38932 )
Change subject: capitalize 'BIOS' ......................................................................
Patch Set 1:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38932/1/Documentation/ifdtool/layou... File Documentation/ifdtool/layout.md:
https://review.coreboot.org/c/coreboot/+/38932/1/Documentation/ifdtool/layou... PS1, Line 45: BIOS
That's the actual output of the tool.
Ack
https://review.coreboot.org/c/coreboot/+/38932/1/Documentation/soc/intel/apo... File Documentation/soc/intel/apollolake/index.md:
https://review.coreboot.org/c/coreboot/+/38932/1/Documentation/soc/intel/apo... PS1, Line 8: bios
That's a name
Ack
Hello Alexander Couzens, Patrick Rudolph, Stefan Reinauer, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38932
to look at the new patch set (#2).
Change subject: capitalize 'BIOS' ......................................................................
capitalize 'BIOS'
Change-Id: I8303b7baa9671f19a036a59775026ffd63c85273 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M Documentation/releases/coreboot-4.8.1-relnotes.md M Documentation/soc/intel/fit.md M Documentation/tutorial/part1.md M payloads/external/SeaBIOS/Kconfig M src/cpu/x86/smm/smm_module_loader.c M src/device/Kconfig M src/device/oprom/include/x86emu/x86emu.h M src/drivers/intel/gma/int15.c M src/mainboard/asus/p8z77-m_pro/cmos.layout M src/mainboard/asus/p8z77-m_pro/early_init.c M src/mainboard/google/cyan/Kconfig M src/mainboard/google/link/mainboard.c M src/mainboard/google/rambi/mainboard.c M src/mainboard/intel/strago/Kconfig M src/mainboard/kontron/ktqm77/mainboard.c M src/mainboard/lenovo/t420/early_init.c M src/soc/intel/apollolake/chip.c M src/soc/intel/common/block/fast_spi/fast_spi.c M src/soc/intel/common/pch/lockdown/lockdown.c M src/soc/intel/skylake/lockdown.c M util/inteltool/inteltool.8 M util/inteltool/spi.c 22 files changed, 30 insertions(+), 30 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/38932/2
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38932 )
Change subject: capitalize 'BIOS' ......................................................................
Patch Set 2: Code-Review+1
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38932 )
Change subject: capitalize 'BIOS' ......................................................................
Patch Set 2: Code-Review+2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38932 )
Change subject: capitalize 'BIOS' ......................................................................
Patch Set 2: Code-Review+2
(2 comments)
https://review.coreboot.org/c/coreboot/+/38932/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38932/2//COMMIT_MSG@7 PS2, Line 7: capitalize 'BIOS' treewide:
https://review.coreboot.org/c/coreboot/+/38932/2/Documentation/tutorial/part... File Documentation/tutorial/part1.md:
https://review.coreboot.org/c/coreboot/+/38932/2/Documentation/tutorial/part... PS2, Line 176: Use the BIOS rom image that we just built. If this flag is left out, the in this case, it's coreboot
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38932 )
Change subject: capitalize 'BIOS' ......................................................................
Patch Set 2:
(2 comments)
Thx
https://review.coreboot.org/c/coreboot/+/38932/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38932/2//COMMIT_MSG@7 PS2, Line 7: capitalize 'BIOS'
treewide:
Done
https://review.coreboot.org/c/coreboot/+/38932/2/Documentation/tutorial/part... File Documentation/tutorial/part1.md:
https://review.coreboot.org/c/coreboot/+/38932/2/Documentation/tutorial/part... PS2, Line 176: Use the BIOS rom image that we just built. If this flag is left out, the
in this case, it's coreboot
Done
Hello Alexander Couzens, Patrick Rudolph, Angel Pons, Paul Menzel, Stefan Reinauer, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38932
to look at the new patch set (#3).
Change subject: treewide: capitalize 'BIOS' ......................................................................
treewide: capitalize 'BIOS'
Also replace 'BIOS' by coreboot when the image is 'coreboot.rom'.
Change-Id: I8303b7baa9671f19a036a59775026ffd63c85273 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M Documentation/releases/coreboot-4.8.1-relnotes.md M Documentation/soc/intel/fit.md M Documentation/tutorial/part1.md M payloads/external/SeaBIOS/Kconfig M src/cpu/x86/smm/smm_module_loader.c M src/device/Kconfig M src/device/oprom/include/x86emu/x86emu.h M src/drivers/intel/gma/int15.c M src/mainboard/asus/p8z77-m_pro/cmos.layout M src/mainboard/asus/p8z77-m_pro/early_init.c M src/mainboard/google/cyan/Kconfig M src/mainboard/google/link/mainboard.c M src/mainboard/google/rambi/mainboard.c M src/mainboard/intel/strago/Kconfig M src/mainboard/kontron/ktqm77/mainboard.c M src/mainboard/lenovo/t420/early_init.c M src/soc/intel/apollolake/chip.c M src/soc/intel/common/block/fast_spi/fast_spi.c M src/soc/intel/common/pch/lockdown/lockdown.c M src/soc/intel/skylake/lockdown.c M util/inteltool/inteltool.8 M util/inteltool/spi.c 22 files changed, 30 insertions(+), 30 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/38932/3
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38932 )
Change subject: treewide: capitalize 'BIOS' ......................................................................
Patch Set 3: Code-Review+2
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38932 )
Change subject: treewide: capitalize 'BIOS' ......................................................................
Patch Set 3:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38932/3/payloads/external/SeaBIOS/K... File payloads/external/SeaBIOS/Kconfig:
https://review.coreboot.org/c/coreboot/+/38932/3/payloads/external/SeaBIOS/K... PS3, Line 126: ps2 later clean up: PS2
https://review.coreboot.org/c/coreboot/+/38932/3/payloads/external/SeaBIOS/K... PS3, Line 131: ps2 again
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38932 )
Change subject: treewide: capitalize 'BIOS' ......................................................................
treewide: capitalize 'BIOS'
Also replace 'BIOS' by coreboot when the image is 'coreboot.rom'.
Change-Id: I8303b7baa9671f19a036a59775026ffd63c85273 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr Reviewed-on: https://review.coreboot.org/c/coreboot/+/38932 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Angel Pons th3fanbus@gmail.com --- M Documentation/releases/coreboot-4.8.1-relnotes.md M Documentation/soc/intel/fit.md M Documentation/tutorial/part1.md M payloads/external/SeaBIOS/Kconfig M src/cpu/x86/smm/smm_module_loader.c M src/device/Kconfig M src/device/oprom/include/x86emu/x86emu.h M src/drivers/intel/gma/int15.c M src/mainboard/asus/p8z77-m_pro/cmos.layout M src/mainboard/asus/p8z77-m_pro/early_init.c M src/mainboard/google/cyan/Kconfig M src/mainboard/google/link/mainboard.c M src/mainboard/google/rambi/mainboard.c M src/mainboard/intel/strago/Kconfig M src/mainboard/kontron/ktqm77/mainboard.c M src/mainboard/lenovo/t420/early_init.c M src/soc/intel/apollolake/chip.c M src/soc/intel/common/block/fast_spi/fast_spi.c M src/soc/intel/common/pch/lockdown/lockdown.c M src/soc/intel/skylake/lockdown.c M util/inteltool/inteltool.8 M util/inteltool/spi.c 22 files changed, 30 insertions(+), 30 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved
diff --git a/Documentation/releases/coreboot-4.8.1-relnotes.md b/Documentation/releases/coreboot-4.8.1-relnotes.md index 8a6ab96..e246236 100644 --- a/Documentation/releases/coreboot-4.8.1-relnotes.md +++ b/Documentation/releases/coreboot-4.8.1-relnotes.md @@ -40,7 +40,7 @@
Lenovo mainboards ----------------- -* Started integration of VBT (Video Bios Table) binary files to +* Started integration of VBT (Video BIOS Table) binary files to support native graphics initialisation
Internal changes diff --git a/Documentation/soc/intel/fit.md b/Documentation/soc/intel/fit.md index 8b638f0..553fef3 100644 --- a/Documentation/soc/intel/fit.md +++ b/Documentation/soc/intel/fit.md @@ -57,4 +57,4 @@ ## References
* [Intel TXT LAB handout](https://downloadmirror.intel.com/18931/eng/Intel%20TXT%20LAB%20Handout.pdf) -* [FIT bios specification](https://www.intel.com/content/dam/www/public/us/en/documents/guides/fit-bios...) +* [FIT BIOS specification](https://www.intel.com/content/dam/www/public/us/en/documents/guides/fit-bios...) diff --git a/Documentation/tutorial/part1.md b/Documentation/tutorial/part1.md index 0c7ef67..7e3da01 100644 --- a/Documentation/tutorial/part1.md +++ b/Documentation/tutorial/part1.md @@ -173,7 +173,7 @@ This starts the QEMU emulator with the i440FX host PCI bridge and PIIX3 PCI to ISA bridge. * `-bios build/coreboot.rom` -Use the bios rom image that we just built. If this flag is left out, the +Use the coreboot rom image that we just built. If this flag is left out, the standard SeaBIOS image that comes with QEMU is used. * `-serial stdio` Send the serial output to the console. This allows you to view the coreboot diff --git a/payloads/external/SeaBIOS/Kconfig b/payloads/external/SeaBIOS/Kconfig index 8ec7361..e816775 100644 --- a/payloads/external/SeaBIOS/Kconfig +++ b/payloads/external/SeaBIOS/Kconfig @@ -125,7 +125,7 @@ level 1 - Basic output, interrupts 5, 18h, 19h, 40h, SMP, PNP, PMM level 2 - AHCI, Floppy, Basic ps2, interrupts 11h, 12h, 14h, 17h level 3 - bootsplash, initializations, SeaBIOS VGA BIOS interrupts - level 4 - bios tables, more optionrom + level 4 - BIOS tables, more optionrom level 5 - Extra bootsplash, more XHCI level 6 - ATA commands, extra optionrom level 7 - extra ps2 commands, more OHCI & EHCI diff --git a/src/cpu/x86/smm/smm_module_loader.c b/src/cpu/x86/smm/smm_module_loader.c index 66a40c4..ca6f611 100644 --- a/src/cpu/x86/smm/smm_module_loader.c +++ b/src/cpu/x86/smm/smm_module_loader.c @@ -396,7 +396,7 @@ /* Does the required amount of memory exceed the SMRAM region size? */ total_size = total_stack_size + handler_size; total_size += fxsave_size + SMM_DEFAULT_SIZE; - // account for the bios resource list + // account for the BIOS resource list if (CONFIG(STM)) total_size += CONFIG_BIOS_RESOURCE_LIST_SIZE;
diff --git a/src/device/Kconfig b/src/device/Kconfig index a25bb91..603c7eb 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -721,7 +721,7 @@
config INTEL_GMA_ADD_VBT depends on SOC_INTEL_COMMON || CPU_INTEL_COMMON - bool "Add a Video Bios Table (VBT) binary to CBFS" + bool "Add a Video BIOS Table (VBT) binary to CBFS" default y if INTEL_GMA_HAVE_VBT help Add a VBT data file to CBFS. The VBT describes the integrated diff --git a/src/device/oprom/include/x86emu/x86emu.h b/src/device/oprom/include/x86emu/x86emu.h index 4ae82d9..e7f48e4 100644 --- a/src/device/oprom/include/x86emu/x86emu.h +++ b/src/device/oprom/include/x86emu/x86emu.h @@ -170,7 +170,7 @@ #define DEBUG_SVC_F 0x000020 #define DEBUG_FS_F 0x000080 #define DEBUG_PROC_F 0x000100 -#define DEBUG_SYSINT_F 0x000200 /* bios system interrupts. */ +#define DEBUG_SYSINT_F 0x000200 /* BIOS system interrupts. */ #define DEBUG_TRACECALL_F 0x000400 #define DEBUG_INSTRUMENT_F 0x000800 #define DEBUG_MEM_TRACE_F 0x001000 diff --git a/src/drivers/intel/gma/int15.c b/src/drivers/intel/gma/int15.c index 7e0ece3..11efe8c 100644 --- a/src/drivers/intel/gma/int15.c +++ b/src/drivers/intel/gma/int15.c @@ -33,7 +33,7 @@ * bit 2 = Graphics Stretching * bit 1 = Text Stretching * bit 0 = Centering (do not set with bit1 or bit2) - * 0 = video bios default + * 0 = video BIOS default */ X86_AX = 0x005f; X86_CX = pfit; diff --git a/src/mainboard/asus/p8z77-m_pro/cmos.layout b/src/mainboard/asus/p8z77-m_pro/cmos.layout index da29d1c..4ac7b5d 100644 --- a/src/mainboard/asus/p8z77-m_pro/cmos.layout +++ b/src/mainboard/asus/p8z77-m_pro/cmos.layout @@ -77,7 +77,7 @@ 421 2 e 8 usb3_mode
# usb3_drv -# Load (or not) pre-OS xHCI USB3 bios driver +# Load (or not) pre-OS xHCI USB3 BIOS driver # 423 1 e 1 usb3_drv
diff --git a/src/mainboard/asus/p8z77-m_pro/early_init.c b/src/mainboard/asus/p8z77-m_pro/early_init.c index 800d975..6c76a7a 100644 --- a/src/mainboard/asus/p8z77-m_pro/early_init.c +++ b/src/mainboard/asus/p8z77-m_pro/early_init.c @@ -115,7 +115,7 @@ .tseg_size = CONFIG_SMM_TSEG_SIZE, .spd_addresses = { 0xa0, 0xa2, 0xa4, 0xa6 }, /* SMBus mul 2 */ .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, - .ec_present = 0, /* Asus 2203 bios shows XUECA016, but no EC */ + .ec_present = 0, /* Asus 2203 BIOS shows XUECA016, but no EC */ .gbe_enable = 0, /* Board uses no Intel GbE but a RTL8111F */ .dimm_channel0_disabled = 0, /* Both DIMM enabled */ .dimm_channel1_disabled = 0, /* Both DIMM enabled */ diff --git a/src/mainboard/google/cyan/Kconfig b/src/mainboard/google/cyan/Kconfig index 6331419..94ffbc0 100644 --- a/src/mainboard/google/cyan/Kconfig +++ b/src/mainboard/google/cyan/Kconfig @@ -78,7 +78,7 @@ depends on VGA_BIOS default "3rdparty/blobs/mainboard/intel/strago/vgabios.bin" help - The C0 version of the video bios gets computed from this name + The C0 version of the video BIOS gets computed from this name so that they can both be added. Only the correct one for the system will be run.
@@ -87,7 +87,7 @@ depends on VGA_BIOS default "8086,22b0" help - The VGA_BIOS_ID for the C0 version of the video bios is hardcoded + The VGA_BIOS_ID for the C0 version of the video BIOS is hardcoded in soc/intel/braswell/Makefile.inc as 8086,22b1
config CBFS_SIZE diff --git a/src/mainboard/google/link/mainboard.c b/src/mainboard/google/link/mainboard.c index 8be4012..32e5487 100644 --- a/src/mainboard/google/link/mainboard.c +++ b/src/mainboard/google/link/mainboard.c @@ -47,10 +47,10 @@ * bit 2 = Graphics Stretching * bit 1 = Text Stretching * bit 0 = Centering (do not set with bit1 or bit2) - * 0 = video bios default + * 0 = video BIOS default */ X86_AX = 0x005f; - X86_CL = 0x00; /* Use video bios default */ + X86_CL = 0x00; /* Use video BIOS default */ res = 1; break; case 0x5f35: @@ -66,7 +66,7 @@ * bit 7 = LFP2 */ X86_AX = 0x005f; - X86_CX = 0x0000; /* Use video bios default */ + X86_CX = 0x0000; /* Use video BIOS default */ res = 1; break; case 0x5f51: diff --git a/src/mainboard/google/rambi/mainboard.c b/src/mainboard/google/rambi/mainboard.c index d4e38d0..7e9b343 100644 --- a/src/mainboard/google/rambi/mainboard.c +++ b/src/mainboard/google/rambi/mainboard.c @@ -48,7 +48,7 @@ * bit 2 = Graphics Stretching * bit 1 = Text Stretching * bit 0 = Centering (do not set with bit1 or bit2) - * 0 = video bios default + * 0 = video BIOS default */ X86_AX = 0x005f; X86_CX = 0x0001; diff --git a/src/mainboard/intel/strago/Kconfig b/src/mainboard/intel/strago/Kconfig index 5e710a5..640f5d4 100644 --- a/src/mainboard/intel/strago/Kconfig +++ b/src/mainboard/intel/strago/Kconfig @@ -35,7 +35,7 @@ depends on VGA_BIOS default "3rdparty/blobs/mainboard/intel/strago/vgabios.bin" help - The C0 version of the video bios gets computed from this name + The C0 version of the video BIOS gets computed from this name so that they can both be added. Only the correct one for the system will be run.
@@ -44,7 +44,7 @@ depends on VGA_BIOS default "8086,22b0" help - The VGA_BIOS_ID for the C0 version of the video bios is hardcoded + The VGA_BIOS_ID for the C0 version of the video BIOS is hardcoded in soc/intel/braswell/Makefile.inc as 8086,22b1
config EC_GOOGLE_CHROMEEC_BOARDNAME diff --git a/src/mainboard/kontron/ktqm77/mainboard.c b/src/mainboard/kontron/ktqm77/mainboard.c index 2af5eb2..5cd3fc4 100644 --- a/src/mainboard/kontron/ktqm77/mainboard.c +++ b/src/mainboard/kontron/ktqm77/mainboard.c @@ -41,12 +41,12 @@ * bit 2 = Graphics Stretching * bit 1 = Text Stretching * bit 0 = Centering (do not set with bit1 or bit2) - * 0 = video bios default + * 0 = video BIOS default */ X86_EAX &= 0xffff0000; X86_EAX |= 0x005f; X86_ECX &= 0xffffff00; - X86_ECX |= 0x00; /* Use video bios default */ + X86_ECX |= 0x00; /* Use video BIOS default */ res = 1; break; case 0x5f35: @@ -64,7 +64,7 @@ X86_EAX &= 0xffff0000; X86_EAX |= 0x005f; X86_ECX &= 0xffff0000; - X86_ECX |= 0x0000; /* Use video bios default */ + X86_ECX |= 0x0000; /* Use video BIOS default */ res = 1; break; case 0x5f51: diff --git a/src/mainboard/lenovo/t420/early_init.c b/src/mainboard/lenovo/t420/early_init.c index 2e39885..c675512 100644 --- a/src/mainboard/lenovo/t420/early_init.c +++ b/src/mainboard/lenovo/t420/early_init.c @@ -48,7 +48,7 @@ pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32); }
-// OC3 set in bios to port 2-7, OC7 set in bios to port 10-13 +// OC3 set in BIOS to port 2-7, OC7 set in BIOS to port 10-13 const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 1, 0 }, /* P0: system port 4, OC0 */ { 1, 1, 1 }, /* P1: system port 2 (EHCI debug), OC 1 */ diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index d9c42f9..b9c5a4f 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -733,7 +733,7 @@ /* Enable Audio clk gate and power gate */ silconfig->HDAudioClkGate = cfg->hdaudio_clk_gate_enable; silconfig->HDAudioPwrGate = cfg->hdaudio_pwr_gate_enable; - /* Bios config lockdown Audio clk and power gate */ + /* BIOS config lockdown Audio clk and power gate */ silconfig->BiosCfgLockDown = cfg->hdaudio_bios_config_lockdown; if (CONFIG(SOC_INTEL_GLK)) glk_fsp_silicon_init_params_cb(cfg, silconfig); diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c index 019976a..49284e9 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi.c @@ -237,7 +237,7 @@
/* LOCAL APIC default address is 0xFEE0000, bios_size over 16MB will * cause memory type conflict when setting memory type to write - * protection, so limit the cached bios region to be no more than 16MB. + * protection, so limit the cached BIOS region to be no more than 16MB. * */ bios_size = MIN(bios_size, 16 * MiB); if (bios_size <= 0) diff --git a/src/soc/intel/common/pch/lockdown/lockdown.c b/src/soc/intel/common/pch/lockdown/lockdown.c index 4a3209e..3fa6e77 100644 --- a/src/soc/intel/common/pch/lockdown/lockdown.c +++ b/src/soc/intel/common/pch/lockdown/lockdown.c @@ -69,12 +69,12 @@ /* Lock FAST_SPIBAR */ fast_spi_lock_bar();
- /* Set Bios Interface Lock, Bios Lock */ + /* Set BIOS Interface Lock, BIOS Lock */ if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) { - /* Bios Interface Lock */ + /* BIOS Interface Lock */ fast_spi_set_bios_interface_lock_down();
- /* Bios Lock */ + /* BIOS Lock */ fast_spi_set_lock_enable(); } } diff --git a/src/soc/intel/skylake/lockdown.c b/src/soc/intel/skylake/lockdown.c index 66dae8c..6911744 100644 --- a/src/soc/intel/skylake/lockdown.c +++ b/src/soc/intel/skylake/lockdown.c @@ -22,7 +22,7 @@
static void lpc_lockdown_config(int chipset_lockdown) { - /* Set Bios Interface Lock, Bios Lock */ + /* Set BIOS Interface Lock, BIOS Lock */ if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) { lpc_set_bios_interface_lock_down(); lpc_set_lock_enable(); diff --git a/util/inteltool/inteltool.8 b/util/inteltool/inteltool.8 index 86a76bd..01e3cfd 100644 --- a/util/inteltool/inteltool.8 +++ b/util/inteltool/inteltool.8 @@ -32,7 +32,7 @@ Dump I/O Controller Hub (ICH) southbridge RCBA registers. .TP .B "-s, --spi" -Dump I/O Controller Hub (ICH) southbridge SPI registers and bios control. +Dump I/O Controller Hub (ICH) southbridge SPI registers and BIOS control. .TP .B "-f, --gfx" .RB "Dump graphics registers. " \ diff --git a/util/inteltool/spi.c b/util/inteltool/spi.c index 22ba3d4..e8289ac 100644 --- a/util/inteltool/spi.c +++ b/util/inteltool/spi.c @@ -22,7 +22,7 @@ { 0x1, 1, "BLE - lock enable" }, { 0x2, 2, "SPI Read configuration" }, { 0x4, 1, "TopSwapStatus" }, - { 0x5, 1, "SMM Bios Write Protect Disable" }, + { 0x5, 1, "SMM BIOS Write Protect Disable" }, { 0x6, 2, "reserved" }, };
-
Angel Pons (Code Review) -
HAOUAS Elyes (Code Review)
-
Patrick Georgi (Code Review)
-
Patrick Rudolph (Code Review)
-
Paul Menzel (Code Review)