Change in coreboot[master]: src/soc/intel/common/itss: Add support to get IRQ configuration for P...
Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34089 )
Change subject: src/soc/intel/common/itss: Add support to get IRQ configuration for PCI devices ......................................................................
Patch Set 10:
(2 comments)
https://review.coreboot.org/c/coreboot/+/34089/10/src/soc/intel/common/block... File src/soc/intel/common/block/itss/Kconfig:
https://review.coreboot.org/c/coreboot/+/34089/10/src/soc/intel/common/block... PS10, Line 8: depends on SOC_INTEL_CANNONLAKE_BASE || SOC_INTEL_ICELAKE
Can this be marked as default n and then in SOC_INTEL_CANNONLAKE_BASE and SOC_INTEL_ICELAKE you can […]
Ack
https://review.coreboot.org/c/coreboot/+/34089/10/src/soc/intel/common/block... File src/soc/intel/common/block/itss/irq.c:
https://review.coreboot.org/c/coreboot/+/34089/10/src/soc/intel/common/block... PS10, Line 108: *num_entries = index;
Just wondering if the IRQ entries exceeds the source buffer capacity, can this *num_entries hold the […]
Ok. Currently FSP would need the pointer the interrupt configuration and the number of IRQ entries in the IRQ configuration that is passed. I would have to update the num_entries with the valid IRQ entries that have been added.
To call out the buffer overrun and by how much it has exceeded, I can add that implementation here, if it helps.
With what I tested 32 IRQ entries should suffice on current platforms. Hatch has 16 valid IRQ entries , based on devicetree selection. I think 32 entries would provide enough buffer.
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Aamir Bohra (Code Review)