Change in coreboot[master]: soc/intel/skylake: Configure ASPM and L1 substates for PCH root ports
Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39538 )
Change subject: soc/intel/skylake: Configure ASPM and L1 substates for PCH root ports ......................................................................
Patch Set 12: Code-Review+1
(1 comment)
Open to the below if it would be considered cleaner. Or alternatives.
"if (config == 0); else if (config)" (the enum would be changed back)
https://review.coreboot.org/c/coreboot/+/39538/6/src/soc/intel/skylake/chip.... File src/soc/intel/skylake/chip.c:
https://review.coreboot.org/c/coreboot/+/39538/6/src/soc/intel/skylake/chip.... PS6, Line 221: PcieRpAspm
With ASPM_DISABLED, coreboot reports that it enabled L1 for ASPM? However, the errors reported by AE […]
No, my mistake. Perhaps a build-time error? In any event, this works as expected.
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Benjamin Doron (Code Review)