Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41520 )
Change subject: soc/intel/tigerlake: Add TCSS devices to soc_acpi_name() ......................................................................
soc/intel/tigerlake: Add TCSS devices to soc_acpi_name()
Add device address and ACPI device names for TCSS devices which were not already defined. The ACPI device names for SSDT generation match those declared in the DSDT at acpi/tcss.asl.
Change-Id: I6a79da7dd78c73345986c12d6ffe467cd4322e05 Signed-off-by: Duncan Laurie dlaurie@google.com --- M src/soc/intel/tigerlake/chip.c M src/soc/intel/tigerlake/include/soc/pci_devs.h 2 files changed, 49 insertions(+), 34 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/41520/1
diff --git a/src/soc/intel/tigerlake/chip.c b/src/soc/intel/tigerlake/chip.c index c1764cd..cf2f143 100644 --- a/src/soc/intel/tigerlake/chip.c +++ b/src/soc/intel/tigerlake/chip.c @@ -57,41 +57,48 @@ return NULL;
switch (dev->path.pci.devfn) { - case SA_DEVFN_ROOT: return "MCHC"; - case PCH_DEVFN_ISH: return "ISHB"; - case PCH_DEVFN_XHCI: return "XHCI"; - case PCH_DEVFN_I2C0: return "I2C0"; - case PCH_DEVFN_I2C1: return "I2C1"; - case PCH_DEVFN_I2C2: return "I2C2"; - case PCH_DEVFN_I2C3: return "I2C3"; - case PCH_DEVFN_I2C4: return "I2C4"; - case PCH_DEVFN_I2C5: return "I2C5"; - case PCH_DEVFN_SATA: return "SATA"; - case PCH_DEVFN_PCIE1: return "RP01"; - case PCH_DEVFN_PCIE2: return "RP02"; - case PCH_DEVFN_PCIE3: return "RP03"; - case PCH_DEVFN_PCIE4: return "RP04"; - case PCH_DEVFN_PCIE5: return "RP05"; - case PCH_DEVFN_PCIE6: return "RP06"; - case PCH_DEVFN_PCIE7: return "RP07"; - case PCH_DEVFN_PCIE8: return "RP08"; - case PCH_DEVFN_PCIE9: return "RP09"; - case PCH_DEVFN_PCIE10: return "RP10"; - case PCH_DEVFN_PCIE11: return "RP11"; - case PCH_DEVFN_PCIE12: return "RP12"; - case PCH_DEVFN_PMC: return "PMC"; - case PCH_DEVFN_UART0: return "UAR0"; - case PCH_DEVFN_UART1: return "UAR1"; - case PCH_DEVFN_UART2: return "UAR2"; - case PCH_DEVFN_GSPI0: return "SPI0"; - case PCH_DEVFN_GSPI1: return "SPI1"; - case PCH_DEVFN_GSPI2: return "SPI2"; - case PCH_DEVFN_GSPI3: return "SPI3"; + case SA_DEVFN_ROOT: return "MCHC"; + case SA_DEVFN_TCSS_XHCI: return "TXHC"; + case SA_DEVFN_TCSS_TDM0: return "TDM0"; + case SA_DEVFN_TCSS_TDM1: return "TDM1"; + case SA_DEVFN_TBT0: return "TRP0"; + case SA_DEVFN_TBT1: return "TRP1"; + case SA_DEVFN_TBT2: return "TRP2"; + case SA_DEVFN_TBT3: return "TRP3"; + case PCH_DEVFN_ISH: return "ISHB"; + case PCH_DEVFN_XHCI: return "XHCI"; + case PCH_DEVFN_I2C0: return "I2C0"; + case PCH_DEVFN_I2C1: return "I2C1"; + case PCH_DEVFN_I2C2: return "I2C2"; + case PCH_DEVFN_I2C3: return "I2C3"; + case PCH_DEVFN_I2C4: return "I2C4"; + case PCH_DEVFN_I2C5: return "I2C5"; + case PCH_DEVFN_SATA: return "SATA"; + case PCH_DEVFN_PCIE1: return "RP01"; + case PCH_DEVFN_PCIE2: return "RP02"; + case PCH_DEVFN_PCIE3: return "RP03"; + case PCH_DEVFN_PCIE4: return "RP04"; + case PCH_DEVFN_PCIE5: return "RP05"; + case PCH_DEVFN_PCIE6: return "RP06"; + case PCH_DEVFN_PCIE7: return "RP07"; + case PCH_DEVFN_PCIE8: return "RP08"; + case PCH_DEVFN_PCIE9: return "RP09"; + case PCH_DEVFN_PCIE10: return "RP10"; + case PCH_DEVFN_PCIE11: return "RP11"; + case PCH_DEVFN_PCIE12: return "RP12"; + case PCH_DEVFN_PMC: return "PMC"; + case PCH_DEVFN_UART0: return "UAR0"; + case PCH_DEVFN_UART1: return "UAR1"; + case PCH_DEVFN_UART2: return "UAR2"; + case PCH_DEVFN_GSPI0: return "SPI0"; + case PCH_DEVFN_GSPI1: return "SPI1"; + case PCH_DEVFN_GSPI2: return "SPI2"; + case PCH_DEVFN_GSPI3: return "SPI3"; /* Keeping ACPI device name coherent with ec.asl */ - case PCH_DEVFN_ESPI: return "LPCB"; - case PCH_DEVFN_HDA: return "HDAS"; - case PCH_DEVFN_SMBUS: return "SBUS"; - case PCH_DEVFN_GBE: return "GLAN"; + case PCH_DEVFN_ESPI: return "LPCB"; + case PCH_DEVFN_HDA: return "HDAS"; + case PCH_DEVFN_SMBUS: return "SBUS"; + case PCH_DEVFN_GBE: return "GLAN"; }
return NULL; diff --git a/src/soc/intel/tigerlake/include/soc/pci_devs.h b/src/soc/intel/tigerlake/include/soc/pci_devs.h index 683172f..b5c598d 100644 --- a/src/soc/intel/tigerlake/include/soc/pci_devs.h +++ b/src/soc/intel/tigerlake/include/soc/pci_devs.h @@ -44,6 +44,14 @@ #define SA_DEVFN_IPU PCI_DEVFN(SA_DEV_SLOT_IPU, 0) #define SA_DEV_IPU PCI_DEV(0, SA_DEV_SLOT_IPU, 0)
+#define SA_DEV_SLOT_TCSS 0x0d +#define SA_DEVFN_TCSS_XHCI PCI_DEVFN(SA_DEV_SLOT_TCSS, 0) +#define SA_DEVFN_TCSS_TDM0 PCI_DEVFN(SA_DEV_SLOT_TCSS, 2) +#define SA_DEVFN_TCSS_TDM1 PCI_DEVFN(SA_DEV_SLOT_TCSS, 3) +#define SA_DEV_TCSS_XHCI PCI_DEV(0, SA_DEV_SLOT_TCSS, 0) +#define SA_DEV_TCSS_TDM0 PCI_DEV(0, SA_DEV_SLOT_TCSS, 2) +#define SA_DEV_TCSS_TDM1 PCI_DEV(0, SA_DEV_SLOT_TCSS, 3) + /* PCH Devices */ #define PCH_DEV_SLOT_SIO0 0x10 #define PCH_DEVFN_CNVI_BT _PCH_DEVFN(SIO0, 2)
Hello Furquan Shaikh, Tim Wawrzynczak, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41520
to look at the new patch set (#2).
Change subject: soc/intel/tigerlake: Add TCSS devices to soc_acpi_name() ......................................................................
soc/intel/tigerlake: Add TCSS devices to soc_acpi_name()
Add ACPI device names for TCSS devices which were not already defined which match those declared in the DSDT at acpi/tcss.asl.
Change-Id: I6a79da7dd78c73345986c12d6ffe467cd4322e05 Signed-off-by: Duncan Laurie dlaurie@google.com --- M src/soc/intel/tigerlake/chip.c 1 file changed, 42 insertions(+), 34 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/41520/2
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41520 )
Change subject: soc/intel/tigerlake: Add TCSS devices to soc_acpi_name() ......................................................................
Patch Set 2: Code-Review+2
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41520 )
Change subject: soc/intel/tigerlake: Add TCSS devices to soc_acpi_name() ......................................................................
Patch Set 2:
Patch Set 1: Verified+1
Build Failed
But jenkins gave +1??
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41520 )
Change subject: soc/intel/tigerlake: Add TCSS devices to soc_acpi_name() ......................................................................
Patch Set 2: Code-Review+2
Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41520
to look at the new patch set (#3).
Change subject: soc/intel/tigerlake: Add TCSS devices to soc_acpi_name() ......................................................................
soc/intel/tigerlake: Add TCSS devices to soc_acpi_name()
Add ACPI device names for TCSS devices which were not already defined which match those declared in the DSDT at acpi/tcss.asl.
Change-Id: I6a79da7dd78c73345986c12d6ffe467cd4322e05 Signed-off-by: Duncan Laurie dlaurie@google.com --- M src/soc/intel/tigerlake/chip.c 1 file changed, 42 insertions(+), 34 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/41520/3
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41520 )
Change subject: soc/intel/tigerlake: Add TCSS devices to soc_acpi_name() ......................................................................
Patch Set 3: Code-Review+2
Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/41520 )
Change subject: soc/intel/tigerlake: Add TCSS devices to soc_acpi_name() ......................................................................
soc/intel/tigerlake: Add TCSS devices to soc_acpi_name()
Add ACPI device names for TCSS devices which were not already defined which match those declared in the DSDT at acpi/tcss.asl.
Change-Id: I6a79da7dd78c73345986c12d6ffe467cd4322e05 Signed-off-by: Duncan Laurie dlaurie@google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/41520 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Furquan Shaikh furquan@google.com --- M src/soc/intel/tigerlake/chip.c 1 file changed, 42 insertions(+), 34 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved
diff --git a/src/soc/intel/tigerlake/chip.c b/src/soc/intel/tigerlake/chip.c index a923074..00db2a4 100644 --- a/src/soc/intel/tigerlake/chip.c +++ b/src/soc/intel/tigerlake/chip.c @@ -58,41 +58,49 @@ return NULL;
switch (dev->path.pci.devfn) { - case SA_DEVFN_ROOT: return "MCHC"; - case PCH_DEVFN_ISH: return "ISHB"; - case PCH_DEVFN_XHCI: return "XHCI"; - case PCH_DEVFN_I2C0: return "I2C0"; - case PCH_DEVFN_I2C1: return "I2C1"; - case PCH_DEVFN_I2C2: return "I2C2"; - case PCH_DEVFN_I2C3: return "I2C3"; - case PCH_DEVFN_I2C4: return "I2C4"; - case PCH_DEVFN_I2C5: return "I2C5"; - case PCH_DEVFN_SATA: return "SATA"; - case PCH_DEVFN_PCIE1: return "RP01"; - case PCH_DEVFN_PCIE2: return "RP02"; - case PCH_DEVFN_PCIE3: return "RP03"; - case PCH_DEVFN_PCIE4: return "RP04"; - case PCH_DEVFN_PCIE5: return "RP05"; - case PCH_DEVFN_PCIE6: return "RP06"; - case PCH_DEVFN_PCIE7: return "RP07"; - case PCH_DEVFN_PCIE8: return "RP08"; - case PCH_DEVFN_PCIE9: return "RP09"; - case PCH_DEVFN_PCIE10: return "RP10"; - case PCH_DEVFN_PCIE11: return "RP11"; - case PCH_DEVFN_PCIE12: return "RP12"; - case PCH_DEVFN_PMC: return "PMC"; - case PCH_DEVFN_UART0: return "UAR0"; - case PCH_DEVFN_UART1: return "UAR1"; - case PCH_DEVFN_UART2: return "UAR2"; - case PCH_DEVFN_GSPI0: return "SPI0"; - case PCH_DEVFN_GSPI1: return "SPI1"; - case PCH_DEVFN_GSPI2: return "SPI2"; - case PCH_DEVFN_GSPI3: return "SPI3"; + case SA_DEVFN_ROOT: return "MCHC"; + case SA_DEVFN_TCSS_XHCI: return "TXHC"; + case SA_DEVFN_TCSS_XDCI: return "TXDC"; + case SA_DEVFN_TCSS_DMA0: return "TDM0"; + case SA_DEVFN_TCSS_DMA1: return "TDM1"; + case SA_DEVFN_TBT0: return "TRP0"; + case SA_DEVFN_TBT1: return "TRP1"; + case SA_DEVFN_TBT2: return "TRP2"; + case SA_DEVFN_TBT3: return "TRP3"; + case PCH_DEVFN_ISH: return "ISHB"; + case PCH_DEVFN_XHCI: return "XHCI"; + case PCH_DEVFN_I2C0: return "I2C0"; + case PCH_DEVFN_I2C1: return "I2C1"; + case PCH_DEVFN_I2C2: return "I2C2"; + case PCH_DEVFN_I2C3: return "I2C3"; + case PCH_DEVFN_I2C4: return "I2C4"; + case PCH_DEVFN_I2C5: return "I2C5"; + case PCH_DEVFN_SATA: return "SATA"; + case PCH_DEVFN_PCIE1: return "RP01"; + case PCH_DEVFN_PCIE2: return "RP02"; + case PCH_DEVFN_PCIE3: return "RP03"; + case PCH_DEVFN_PCIE4: return "RP04"; + case PCH_DEVFN_PCIE5: return "RP05"; + case PCH_DEVFN_PCIE6: return "RP06"; + case PCH_DEVFN_PCIE7: return "RP07"; + case PCH_DEVFN_PCIE8: return "RP08"; + case PCH_DEVFN_PCIE9: return "RP09"; + case PCH_DEVFN_PCIE10: return "RP10"; + case PCH_DEVFN_PCIE11: return "RP11"; + case PCH_DEVFN_PCIE12: return "RP12"; + case PCH_DEVFN_PMC: return "PMC"; + case PCH_DEVFN_UART0: return "UAR0"; + case PCH_DEVFN_UART1: return "UAR1"; + case PCH_DEVFN_UART2: return "UAR2"; + case PCH_DEVFN_GSPI0: return "SPI0"; + case PCH_DEVFN_GSPI1: return "SPI1"; + case PCH_DEVFN_GSPI2: return "SPI2"; + case PCH_DEVFN_GSPI3: return "SPI3"; /* Keeping ACPI device name coherent with ec.asl */ - case PCH_DEVFN_ESPI: return "LPCB"; - case PCH_DEVFN_HDA: return "HDAS"; - case PCH_DEVFN_SMBUS: return "SBUS"; - case PCH_DEVFN_GBE: return "GLAN"; + case PCH_DEVFN_ESPI: return "LPCB"; + case PCH_DEVFN_HDA: return "HDAS"; + case PCH_DEVFN_SMBUS: return "SBUS"; + case PCH_DEVFN_GBE: return "GLAN"; }
return NULL;
9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41520 )
Change subject: soc/intel/tigerlake: Add TCSS devices to soc_acpi_name() ......................................................................
Patch Set 4:
Automatic boot test returned (PASS/FAIL/TOTAL): 4/0/4 Emulation targets: "QEMU x86 q35/ich9" using payload TianoCore : SUCCESS : https://lava.9esec.io/r/3695 "QEMU x86 q35/ich9" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/3694 "QEMU x86 i440fx/piix4" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/3693 "QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/3692
Please note: This test is under development and might not be accurate at all!
-
9elements QA (Code Review) -
Duncan Laurie (Code Review)
-
Furquan Shaikh (Code Review)
-
Tim Wawrzynczak (Code Review)