Patch merged into coreboot/master: arch/x86: introduce postcar stage/phase

the following patch was just integrated into master:
commit 7f8afe063139f6fc7076a3e4edf6093a953792dc
Author: Aaron Durbin 
Date:   Fri Mar 18 12:21:23 2016 -0500

arch/x86: introduce postcar stage/phase

Certain chipsets don't have a memory-mapped boot media
    so their code execution for stages prior to DRAM initialization
    is backed by SRAM or cache-as-ram. The postcar stage/phase
    handles the cache-as-ram situation where in order to tear down
    cache-as-ram one needs to be executing out of a backing
    store that isn't transient. By current definition, cache-as-ram
    is volatile and tearing it down leads to its contents disappearing.
    Therefore provide a shim layer, postcar, that's loaded into
    memory and executed which does 2 things:

1. Tears down cache-as-ram with a chipset helper function.
    2. Loads and runs ramstage.

Because those 2 things are executed out of ram there's no issue
    of the code's backing store while executing the code that
    tears down cache-as-ram. The current implementation makes no
    assumption regarding cacheability of the DRAM itself. If the
    chipset code wishes to cache DRAM for loading of the postcar
    stage/phase then it's also up to the chipset to handle any
    coherency issues pertaining to cache-as-ram destruction.

Change-Id: Ia58efdadd0b48f20cfe7de2f49ab462306c3a19b
    Signed-off-by: Aaron Durbin 
    Reviewed-on: https://review.coreboot.org/14140
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi 
    Reviewed-by: Furquan Shaikh

See https://review.coreboot.org/14140 for details.

-gerrit