Change in coreboot[master]: soc/intel/alderlake: Enable VT-d

[Meera Ravindranath (Code Review)]

Attention is currently required from: Furquan Shaikh, Maulik V Vaghela, Tim Wawrzynczak, Ronak Kanabar, Patrick Rudolph.
Meera Ravindranath has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51849 )

Change subject: soc/intel/alderlake: Enable VT-d
......................................................................

Patch Set 7:

(1 comment)

File src/soc/intel/alderlake/romstage/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/51849/comment/958a4b78_5c6262ac 
PS6, Line 198: m_cfg->VtdDisable = 0;
             : 	m_cfg->VtdIopEnable = 0x1;
             : 
             : 	if (m_cfg->InternalGfx && GFXVT_BASE_ADDRESS == 0) {
             : 		m_cfg->VtdIgdEnable = 0;
             : 		printk(BIOS_ERR, "ERROR: Requested IGD VT-d, but GFXVT_BASE_ADDRESS is 0\n");
             : 	}
             : 	else {
             : 		m_cfg->VtdIgdEnable = 0x1;
             : 		m_cfg->VtdBaseAddress[0] = GFXVT_BASE_ADDRESS;
             : 	}
             : 
             : 	if (m_cfg->SaIpuEnable && IPUVT_BASE_ADDRESS == 0) {
             : 		m_cfg->VtdIpuEnable = 0x0;
             : 		printk(BIOS_ERR, "ERROR: Requested IPU VT-d, but IPUVT_BASE_ADDRESS is 0\n");
             : 	}
             : 	else {
             : 		m_cfg->VtdIpuEnable = 0x1;
             : 		m_cfg->VtdBaseAddress[1] = IPUVT_BASE_ADDRESS;
             : 	}
> Let's try to be consistent when specifying boolean values, e.g. […]

Done