Johnny Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41278 )
Change subject: soc/xeon_sp/cpx: Define MSR PPIN related registers ......................................................................
soc/xeon_sp/cpx: Define MSR PPIN related registers
These changes are in accordance with the documentation: [*] page 208-209 Intel(R) 64 and IA-32 Architectures, Software Developer’s Manual, Volume 4: Model-Specific Registers. May 2019. Order Number: 335592-070US
Tested on OCP DeltaLake with change https://review.coreboot.org/c/coreboot/+/40308/
Signed-off-by: Johnny Lin johnny_lin@wiwynn.com Change-Id: I87134b2e98c9b0c031be9375b75a2aa1284ae9bb --- M src/soc/intel/xeon_sp/cpx/include/soc/msr.h 1 file changed, 9 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/41278/1
diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/msr.h b/src/soc/intel/xeon_sp/cpx/include/soc/msr.h index 6004490..b3eede7 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/msr.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/msr.h @@ -110,4 +110,13 @@ #define EPB_ENERGY_POLICY_SHIFT 3 #define EPB_ENERGY_POLICY_MASK (0xf << EPB_ENERGY_POLICY_SHIFT)
+/* MSR Protected Processor Inventory Number */ +#define MSR_PPIN_CTL 0x04e +#define MSR_PPIN_CTL_LOCK 0x1 +#define MSR_PPIN_CTL_ENABLE_SHIFT 1 +#define MSR_PPIN_CTL_ENABLE (0x1 << MSR_PPIN_CTL_ENABLE_SHIFT) +#define MSR_PPIN 0x04f +#define MSR_PPIN_CAP_SHIFT 23 +#define MSR_PPIN_CAP (0x1 << MSR_PPIN_CAP_SHIFT) + #endif /* _SOC_MSR_H_ */
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41278 )
Change subject: soc/xeon_sp/cpx: Define MSR PPIN related registers ......................................................................
Patch Set 1: Code-Review+2
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41278 )
Change subject: soc/xeon_sp/cpx: Define MSR PPIN related registers ......................................................................
Patch Set 1: Code-Review+2
Hello build bot (Jenkins), Maxim Polyakov, Jonathan Zhang, David Hendricks, Jingle Hsu, Morgan Jang, Andrey Petrov, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41278
to look at the new patch set (#3).
Change subject: soc/xeon_sp/cpx: Define MSR PPIN related registers ......................................................................
soc/xeon_sp/cpx: Define MSR PPIN related registers
These changes are in accordance with the documentation: [*] page 208-209 Intel(R) 64 and IA-32 Architectures, Software Developer’s Manual, Volume 4: Model-Specific Registers. May 2019. Order Number: 335592-070US
Tested on OCP DeltaLake with change https://review.coreboot.org/c/coreboot/+/40308/
Signed-off-by: Johnny Lin johnny_lin@wiwynn.com Change-Id: I87134b2e98c9b0c031be9375b75a2aa1284ae9bb --- M src/soc/intel/xeon_sp/cpx/include/soc/msr.h 1 file changed, 9 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/41278/3
Hello build bot (Jenkins), Maxim Polyakov, Jonathan Zhang, David Hendricks, Jingle Hsu, Morgan Jang, Andrey Petrov, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41278
to look at the new patch set (#5).
Change subject: soc/xeon_sp/cpx: Define MSR PPIN related registers ......................................................................
soc/xeon_sp/cpx: Define MSR PPIN related registers
These changes are in accordance with the documentation: [*] page 208-209 Intel(R) 64 and IA-32 Architectures, Software Developer’s Manual, Volume 4: Model-Specific Registers. May 2019. Order Number: 335592-070US
Tested on OCP DeltaLake with change https://review.coreboot.org/c/coreboot/+/40308/
Signed-off-by: Johnny Lin johnny_lin@wiwynn.com Change-Id: I87134b2e98c9b0c031be9375b75a2aa1284ae9bb --- M src/soc/intel/xeon_sp/cpx/include/soc/msr.h 1 file changed, 9 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/41278/5
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/41278 )
Change subject: soc/xeon_sp/cpx: Define MSR PPIN related registers ......................................................................
soc/xeon_sp/cpx: Define MSR PPIN related registers
These changes are in accordance with the documentation: [*] page 208-209 Intel(R) 64 and IA-32 Architectures, Software Developer’s Manual, Volume 4: Model-Specific Registers. May 2019. Order Number: 335592-070US
Tested on OCP DeltaLake with change https://review.coreboot.org/c/coreboot/+/40308/
Signed-off-by: Johnny Lin johnny_lin@wiwynn.com Change-Id: I87134b2e98c9b0c031be9375b75a2aa1284ae9bb Reviewed-on: https://review.coreboot.org/c/coreboot/+/41278 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Patrick Rudolph siro@das-labor.org Reviewed-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/soc/intel/xeon_sp/cpx/include/soc/msr.h 1 file changed, 9 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved Maxim Polyakov: Looks good to me, approved
diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/msr.h b/src/soc/intel/xeon_sp/cpx/include/soc/msr.h index f9d59f1..922bce9 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/msr.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/msr.h @@ -96,4 +96,13 @@ #define EPB_ENERGY_POLICY_SHIFT 3 #define EPB_ENERGY_POLICY_MASK (0xf << EPB_ENERGY_POLICY_SHIFT)
+/* MSR Protected Processor Inventory Number */ +#define MSR_PPIN_CTL 0x04e +#define MSR_PPIN_CTL_LOCK 0x1 +#define MSR_PPIN_CTL_ENABLE_SHIFT 1 +#define MSR_PPIN_CTL_ENABLE (0x1 << MSR_PPIN_CTL_ENABLE_SHIFT) +#define MSR_PPIN 0x04f +#define MSR_PPIN_CAP_SHIFT 23 +#define MSR_PPIN_CAP (0x1 << MSR_PPIN_CAP_SHIFT) + #endif /* _SOC_MSR_H_ */
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Johnny Lin (Code Review) -
Maxim Polyakov (Code Review)
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Patrick Georgi (Code Review)
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Patrick Rudolph (Code Review)