Change in coreboot[master]: mb/intel/adlrvp: Add support for new board

[Maulik V Vaghela (Code Review)]

Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55486 )

Change subject: mb/intel/adlrvp: Add support for new board
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mb/intel/adlrvp: Add support for new board

Adding support for new ADLRVP LP5 board with board ID 0x33.

TEST=Check if board boots with upstream coreboot with this patch

Change-Id: Id64677e5b8aee174182beaa86666637149fc7ef4
Signed-off-by: Maulik V Vaghela 
---
M src/mainboard/intel/adlrvp/include/baseboard/variants.h
M src/mainboard/intel/adlrvp/mainboard.c
M src/mainboard/intel/adlrvp/memory.c
M src/mainboard/intel/adlrvp/romstage_fsp_params.c
4 files changed, 4 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/55486/1

diff --git a/src/mainboard/intel/adlrvp/include/baseboard/variants.h b/src/mainboard/intel/adlrvp/include/baseboard/variants.h
index 9a94db2..810fe70 100644
--- a/src/mainboard/intel/adlrvp/include/baseboard/variants.h
+++ b/src/mainboard/intel/adlrvp/include/baseboard/variants.h
@@ -18,6 +18,7 @@
    /* ADL-P LPDDR5 RVP */
    ADL_P_LP5_1 = 0x13,
    ADL_P_LP5_2 = 0x17,
+	ADL_P_LP5_3 = 0x33,
    /* ADL-P DDR4 RVPs */
    ADL_P_DDR4_1 = 0x14,
    ADL_P_DDR4_2 = 0x3F,
diff --git a/src/mainboard/intel/adlrvp/mainboard.c b/src/mainboard/intel/adlrvp/mainboard.c
index eb86773..64c3413 100644
--- a/src/mainboard/intel/adlrvp/mainboard.c
+++ b/src/mainboard/intel/adlrvp/mainboard.c
@@ -46,6 +46,7 @@
    switch (sku_id) {
    case ADL_P_LP5_1:
    case ADL_P_LP5_2:
+	case ADL_P_LP5_3:
    	return "vbt_adlrvp_lp5.bin";
    case ADL_P_DDR5_1:
    case ADL_P_DDR5_2:
diff --git a/src/mainboard/intel/adlrvp/memory.c b/src/mainboard/intel/adlrvp/memory.c
index 353cf4e..796fa88 100644
--- a/src/mainboard/intel/adlrvp/memory.c
+++ b/src/mainboard/intel/adlrvp/memory.c
@@ -305,6 +305,7 @@
    	return &ddr5_mem_config;
    case ADL_P_LP5_1:
    case ADL_P_LP5_2:
+	case ADL_P_LP5_3:
    	return &lp5_mem_config;
    case ADL_M_LP4:
    	return &adlm_lp4_mem_config;
diff --git a/src/mainboard/intel/adlrvp/romstage_fsp_params.c b/src/mainboard/intel/adlrvp/romstage_fsp_params.c
index 9fff257..b743d7c 100644
--- a/src/mainboard/intel/adlrvp/romstage_fsp_params.c
+++ b/src/mainboard/intel/adlrvp/romstage_fsp_params.c
@@ -60,6 +60,7 @@
    case ADL_P_LP4_2:
    case ADL_P_LP5_1:
    case ADL_P_LP5_2:
+	case ADL_P_LP5_3:
    case ADL_M_LP4:
    case ADL_M_LP5:
    	memcfg_init(&mupd->FspmConfig, mem_config, &lp4_lp5_spd_info, half_populated);