Attention is currently required from: Furquan Shaikh, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56175 )
Change subject: soc/intel/alderlake: Add (and fix) devices in IRQ table ......................................................................
Patch Set 2:
(1 comment)
File src/soc/intel/alderlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/56175/comment/7c26a20a_1a6ee51a PS2, Line 51: FIXED_INT_PIRQ
Just curious: Is this requirement in the BWG? Or how was it determined that some of these devies req […]
EDS and both say INT_LINE is RW for IGD and IPU (and indeed, they appear programmable from lspci's reporting), but empirically, S0ix fails if they are not set to 16 (their pin is RO set to PCI_INT_A).
The CPU_6 slot is just more PCIe RPs, so are programmed the same as the the PCH side (according to their `function number % 4`)
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Tim Wawrzynczak (Code Review)