Anil Kumar K has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/77683?usp=email )
Change subject: commonlib: Add new "CSE EDP PHY load" TS ......................................................................
commonlib: Add new "CSE EDP PHY load" TS
Signed-off-by: Anil Kumar anil.kumar.k@intel.com Change-Id: Ie932c17edccd26dd323350600446bed325e62b91 --- M src/commonlib/include/commonlib/timestamp_serialized.h 1 file changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/77683/1
diff --git a/src/commonlib/include/commonlib/timestamp_serialized.h b/src/commonlib/include/commonlib/timestamp_serialized.h index d0ecd8f..7923ead 100644 --- a/src/commonlib/include/commonlib/timestamp_serialized.h +++ b/src/commonlib/include/commonlib/timestamp_serialized.h @@ -144,6 +144,8 @@ /* 990+ reserved for vendorcode extensions (990-999: Intel ME continued) */ TS_ME_ROM_START = 990, TS_ISSE_DMU_LOAD_END = 991, + TS_CSE_EDP_PHY_LOAD_START = 992, + TS_CSE_EDP_PHY_LOAD_END = 993,
/* 1000+ reserved for payloads */
@@ -334,6 +336,8 @@ /* Intel ME continued */ TS_NAME_DEF(TS_ME_ROM_START, 0, "CSME ROM started execution"), TS_NAME_DEF(TS_ISSE_DMU_LOAD_END, 0, "Die Management Unit (DMU) load completed"), + TS_NAME_DEF(TS_CSE_EDP_PHY_LOAD_START, 0, "CSE EDP PHY load start"), + TS_NAME_DEF(TS_CSE_EDP_PHY_LOAD_END, 0, "CSE EDP PHY load Done"),
/* Depthcharge entry timestamp */ TS_NAME_DEF(TS_DC_START, 0, "depthcharge start"),