Change in coreboot[master]: mb/google/mancomb: Add ACPI support for Chrome EC

[Raul Rangel (Code Review)]

Raul Rangel has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51628 )

Change subject: mb/google/mancomb: Add ACPI support for Chrome EC
......................................................................

mb/google/mancomb: Add ACPI support for Chrome EC

BUG=b:182211161
TEST=builds

Signed-off-by: Eric Lai 
Change-Id: Ibce15d2e4340515353a33c593d065df50a15286a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51628
Tested-by: build bot (Jenkins) 
Reviewed-by: Mathew King 
---
M src/mainboard/google/mancomb/dsdt.asl
M src/mainboard/google/mancomb/variants/baseboard/devicetree.cb
2 files changed, 16 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Mathew King: Looks good to me, approved

diff --git a/src/mainboard/google/mancomb/dsdt.asl b/src/mainboard/google/mancomb/dsdt.asl
index 7b8982a..73a2ea5 100644
--- a/src/mainboard/google/mancomb/dsdt.asl
+++ b/src/mainboard/google/mancomb/dsdt.asl
@@ -1,6 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-only */

#include <acpi/acpi.h>
+#include <variant/ec.h>
+
 DefinitionBlock (
    "dsdt.aml",
    "DSDT",
@@ -13,4 +15,13 @@
    #include <acpi/dsdt_top.asl>

#include <soc.asl>
+
+	/* Chrome OS Embedded Controller */
+	Scope (_SB.PCI0.LPCB)
+	{
+		/* ACPI code for EC SuperIO functions */
+		#include <ec/google/chromeec/acpi/superio.asl>
+		/* ACPI code for EC functions */
+		#include <ec/google/chromeec/acpi/ec.asl>
+	}
 }
diff --git a/src/mainboard/google/mancomb/variants/baseboard/devicetree.cb b/src/mainboard/google/mancomb/variants/baseboard/devicetree.cb
index db21dd4..c4ef3f5 100644
--- a/src/mainboard/google/mancomb/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/mancomb/variants/baseboard/devicetree.cb
@@ -42,5 +42,10 @@
    	device ref gpp_bridge_a on  # Internal GPP Bridge 0 to Bus A
    		device ref gfx on end # Internal GPU (GFX)
    	end
+		device ref lpc_bridge on
+			chip ec/google/chromeec
+				device pnp 0c09.0 on end
+			end
+		end
    end # domain
 end	# chip soc/amd/cezanne